Electric Clock for NanoMagnet Logic Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 74

A) B C

E)

F)

D)

Fig. 3. Clocking mechanism for NML technology. (A) Starting from an initial config-
uration, (B) the value of the input element change and the other magnets are forced
in the RESET state by an external mean, like a magnetic field. (C)-(F) When the
magnetic field is removed magnets realign themselves following the input element,
propagating therefore the information through the circuit.

Fig. 4. 3-phase clock system. (A) Clock signal waveforms. 3 clock signals, with a phase
difference of 120 ◦ , are used to assure a correct signals propagation. (B) Detailed signal
propagation through a simple NML wire. When magnets of a clock zone are switching
(SWITCH) magnets on their left are in the HOLD state and act as an input, while
magnets on their right are in the RESET state so they have no influence.

1.1 Comparison of Main Clock Solutions

Clocking is the most important feature of NML circuits, giving them a char-
acteristic pipelined behavior [ 23 - 25 ] that represents a considerable source of
problems. The most important of these problems is power consumption. While
the intrinsic power consumption of NML circuits is extremely low [ 18 ] the losses
in the clock generation system can be quite high, wiping out one of the major
advantages of NML technology.
Different clock systems have been proposed. The first of this mechanisms is
shown in Fig. 5 (A). A magnetic field directed along the shorter magnets side is
generated by a current flowing through a wire placed under the magnets plane.
The wire, made of copper, is buried in a ferrite yoke to obtain a better distri-
bution of the magnetic flux lines. This system works and it has already been
theoretically demonstrated [ 26 ], however its power consumption is very high.
In [ 11 ] a current of 545 mA on a wire 1

m wide was necessary to successfully
reset magnets. A magnetic field is also used in another NML implementation,

µ