Electric Clock for NanoMagnet Logic Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 73

WIRE

INPUTS

A)

INPUT OUTPUT

AND OR

MAJORITY
VOTER

B) C)

INVERTER D)

Fig. 2. NML basic logic gates. (A) Wire. (B) Inverter. It is made simply using a wire
with an odd number of magnets. (C) Majority voter. The value of the central magnets
is equal to the majority of the inputs. (D) AND/OR gates built changing the shape of
the central magnet.

function, its asymmetry may cause errors in the signal propagation as shown in
[ 15 , 16 ]. However, it is possible to expand the logic set available implementing
two inputs AND/OR gates, that are shown in Fig. 2 (D). Changing the shape of
the central magnet gives it a preferential state, so that only when both magnets
are up or down they are able to influence the central magnet [ 17 ].
Unfortunately the magnetic field generated by a magnet is not strong enough
to switch its neighbors. As a consequence an external mean, like an external
magnetic field, is necessary to help magnets switching [ 18 - 20 ]. Considering for
example the simple QCA wire of Fig. 3 (A), if only the input magnet is switched
from '1' to '0' (Fig. 3 ) the second magnet will remain in the same state without
switching. However an external magnetic field can be applied to force the other
magnets in the RESET state (Fig. 3 (B)). The RESET state is an unstable state
so, when the magnetic field is removed, the first magnets will switch according to
the input element, while the other magnets will remain temporary in the RESET
state (Fig. 3 (C)). Magnets will therefore switch one by one (Fig. 3 from (D) to
(E)) with a domino-like effect, therefore propagating the new input value.
As demonstrated in [ 21 , 22 ] only a limited number of magnets can be cascaded
without errors generation during the realignment phase. Consequently, in order
to build complex circuits a multiphase clock system must be used. Circuits are
divided in small areas, called clock zones, each of them made by a limited number
of magnets. At each clock zones a different clock signal is applied. For example
in Fig. 4 a 3 phase clock system is depicted. Each clock zone is subjected to
one of the three clock signals showed in Fig. 4 (A). The clock waveform is always
the same, but signals have a phase difference of 120 ⓦ . The circuit state evolution
is showed in Fig. 4 (B). When magnets belonging to a clock zone are in the
SWITCH state, that means the magnetic field is slowly removed, magnets on the
clock zone on their left are in the HOLD phase (no magnetic field applied) and
act like an input. Magnets in the clock zone on their right are in the RESET state,
so they have no influence on the signals propagation. Thanks to this mechanism
signals propagate correctly in a specific direction.