Reversible and Adiabatic Computing: Energy-Efficiency Maximized - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 340

is shown if Fig. 1 (b) with the corresponding dual-clock waveforms in Fig. 1 (c), which
can input energy into the circuit and recover it back. The adiabatic energy loss is

E adiabatic ¼ RC 2 V DD 2 = t ramp ;

ð 2 Þ

where t ramp is the time duration of the ramp. It should be noted that the split-rail
signals ensure that the circuit does not lose the typical minimum energy E t ¼ 1 = 2 CV t
associated with the transistor threshold drop V t , which a single-rail approach would
lose. The pipelining of this type of asymptotically adiabatic logic, where there is no
lower bound on the dissipation, is challenging due to the need to utilize reversible
gates or include garbage signals. For an introduction to adiabatic circuit families and
their classification the reader is referred to [ 13 ], which describes also quasi-adiabatic
approaches enabling simple pipelining but losing some part of the energy. Our design
differs from the previous circuits [ 12 , 14 - 16 ], since it has no logic overhead for the
reversibility, utilizing the Bennett-clocking scheme described in the next section.

2.2 Reversible Logic and Operations

While the circuits presented here are based on adiabatic operation, we believe that
maintaining a high degree of energy conservation requires either reversible logic gates
or an operating principle that implements logical reversibility. Fully reversible circuits
can be constructed using reversible logic gates, like the Toffoli gate [ 17 ], but this
results in large circuit area and many ''garbage'' signals needed to retain the state
throughout the computation. Another alternative is to utilize Bennett-clocking [ 18 ],
where the logic structure of the circuit remains unmodified, but the timing is altered to
include a compute step and a de-compute step, at the cost of reduced pipelining and
throughput. Recovering the signal energy to any desired extent is possible using
asymptotically adiabatic logic, where the energy is transferred inside the circuit
avoiding any abrupt charging or discharging of the circuit nodes. However, designing
such circuits implies that the utilized logic operations have to be reversible in nature.
Logical reversibility is connected to the physical reversibility of the system, that
is, the physical, thermodynamically described state of the system has to mirror to
some degree the computation that is performed. Fifty years ago, Rolf Landauer pro-
posed this connection in [ 9 ] and the Landauer's Principle was confirmed with a
generic one-bit memory experiment recently reported in [ 10 ]. A bit erasure at the
room temperature has an inevitable energy cost of at least 3 zJ, which usually must
be dissipated as heat into the environment. This part of the signal energy cannot be
adiabatically recovered, unless we incorporate logical reversibility into the circuit.
In traditional circuits the bit erasure energy is insignificant compared to the other
losses. For example, the end-of-the-roadmap CMOS will dissipate about three orders
of magnitude higher energy per switching event since it loses the full signal energy at
each switching event [ 1 ]. Losses in the emerging technologies like quantum-dot
cellular automata (QCA) [ 2 ] vary, but not counting the information loss, the dissi-
pation in all of them is like friction in nature: it can be made as small as desired by
switching more slowly, while the energy-per-bit-erasure is unaffected by the speed.