Information Technology Reference
In-Depth Information
circuit node. Most of this loss can be avoided by utilizing adiabatic charging prin-
ciples, which can be fully implemented only by logically reversible circuits. Logically
reversible circuits save energy by avoiding the bit erasures and the related heat, but in
addition, these circuits have to avoid the other types of loss, like static leakage and
dynamic signal energy loss related to the switching mechanism. The operating prin-
ciple must not lead to the loss of all signal energy during every switching event, like in
traditional CMOS. One key property in QCA and NML is the signal energy conser-
vation: the cells settle to the ground state while the signal energy is transmitted from
cell to cell. In these technologies, the loss is low and the signal level high [
2
,
3
].
2.1
Adiabatic Charging
Adiabatic charging is one of the pre-requisites of practical reversible circuits. For
QCA, this implies that the clock field potentials must be switched at a lower rate than
the highest possible rate of the cellular automata. The predicted terahertz devices
would have adiabatic switching speeds of tens to hundreds of gigahertz. This is a
speed vs. power tradeoff.
The energy dissipation in standard circuits occurs when electrical currents are
driven through transistors, with a finite on-resistance, and resistive signal lines. The
resistive losses are proportional to the voltage drop, for example between the termi-
nals of a transistor device, which points to an approach of limiting this voltage
difference and avoiding abrupt currents as a means to limit dissipation. For example, a
static CMOS inverter gate in Fig.
1
(a) represents information by the output node
voltage, and dissipates all of the signal energy at each switching operation. During a
switching event, either the pull-up or pull-down network loses
E
CMOS
¼
1
=
2
CV
DD
2
;
ð
1
Þ
where C is the output node capacitance including the wiring and next gate input, and
V
DD
is the operating voltage. This energy is practically all the signal energy.
This circuit can be modified to recover signal energy by utilizing ramped power-
clock signals instead of the static operating voltage and ground. An example of such
energy-recovering 1n1p-logic, or Split-Level Charge Recovery Logic [
11
,
12
] inverter
V
DD
a
a
a
a
C
C
Fig. 1. CMOS inverter. (a) Standard static CMOS implementation, (b) adiabatic 1n1p CMOS
implementation, and (c) dual-rail power-clock.
Search WWH ::
Custom Search