Information Technology Reference
In-Depth Information
Fan-Out Management.
As in the case of CMOS technology, also NML has a
limitation on the fan-out that each cell can support. The main reasons are related
to NML clock zones dimensions, to the physical space occupied by the wires
and to the number of magnets that can be cascaded inside a clock zone. With
a parallel clock zones layout organization, the vertical magnetic wires length
should be limited in order to avoid propagation errors. Besides, considering that
each wire is made by magnets there must be enough space to allow their physical
placement. Therefore, the input graph is iteratively analyzed and mapped into
a new one where the fan-out limit is satisfied.
Reconvergent Paths Balance.
The graph generated starting from a circuit
netlist can present many
reconvergent paths
. Two paths, in a direct acyclic graph
(DAG), are called
reconvergent
if they diverge from and reconverge to the same
blocks. This situation is common with traditional technology, but with NML it
can generate some problems due to its intrinsic pipelined behavior that origi-
nates the so called “layout = timing” problem. In order to guarantee signals
synchronization at the input of each logic gate, additional intermediate nodes
must be added, so that all the reconvergent paths are composed by the same
number of nodes.
Cross-Wires Minimization.
Since NML is a planar technology, up to now just
one layer can be used to build a circuit. A particular component, called
cross-
wire
, is available to cross two wires on the same plane without interferences. Even
if this block allows physical wires intersection a specific optimization is needed to
reduce the number of cross-wire, therefore the wasted area. Different techniques
are here implemented, such as
Barycenter
,
Fan-out Tolerance Duplication
,
Sim-
ulated Annealing
and
Kernighan-Lin
. They can be used alone or combining one
or more of them together.
Barycenter.
The basic idea behind this method is to rearrange nodes in order to
place them directly above the nodes to which they are connected. The algorithm
explores each rows of the graph two by two from inputs to outputs. For each
couple of rows analyzed one is kept frozen while nodes in the other row are
changed in position to reduce the number of cross-wires. This algorithm is quite
simple and fast but leads to an unoptimized result. This is due because there can
be situation in which multiple solutions satisfy the requisites of the algorithm.
This solutions have however a different number of cross-wires, so the eciency
of the algorithm heavily depends on the policy chosen to solve this conflicting
situations.
Fan-out Duplication.
The job of the fan-out duplication algorithm is to integrate
the
Barycenter
method in order to reduce wire crosses. As can be gathered from
the name of this technique, graph nodes are duplicated trying to reduce the
cross-wires number. The number of cross-wires can be theoretically reduced to
0, however the circuit area grows exponentially.
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