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NML technology issues. What is new is how these algorithms are used together
in order to obtain a final layout compliant with the technology constrains and
limitations. The proposed NML design flow can be divided in two main parts:
graph elaboration and physical mapping, which will be discussed in the follow-
ing sections. The algorithm is divided in two parts,
Graph Elaboration
where the
graph generated by the parser is optimized (see Sect.
4.1
)and
Physical Mapping
where the circuit layout is generated (described in Sect.
4.2
).
4.1 Graph Elaboration
The flow diagram of the graph elaboration phase is shown in Fig.
12
. Starting
from a structural description of the circuit, mapped on a set of cells available
(majority voter, and, or, inverter), the HDL parser generates a graph which is
the primary input of the place and route engine.
Fig. 12.
Graph Elaboration flow diagram. The entry point is the graph generated by
the parser while the output is an optimized graph used to create the circuit layout.
Several optimizations are performed on the input graph, each part of the algorithm
can be customized using appropriate parameters.
This data structure is then handled according to NML characteristics and
the clock zones layout. The operations performed by these algorithms can be
summarized as:
-
Fan-out management
, the graph is modified to take into account a limited
fan-out, given as a parameter, for each graph node.
-
Reconvergent paths balance
, paths inside the graph are balanced to avoid “lay-
out=timing” problems.
-
Wire crossing minimization
, the graph is elaborated using various algorithms
(customizable with several input parameters) to reduce the number of wires-
crossing.
At the end of this process the output graph is used as input for the physi-
cal mapping phase. In the following a detailed description of each algorithm is
reported.
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