Information Technology Reference
In-Depth Information
4. Walus, K., Jullien, G.A.: Design tools for an emerging soc technology: quantum-dot
cellular automata. Proc. IEEE 94 (6), 1225-1244 (2006)
5. Smith, C., Gardelis, S., Rushforth, A., Crook, R., Cooper, J., Ritchie, D.,
Linfield, E., Jin, Y., Pepper, M.: Realization of quantum-dot cellular automata
using semiconductor quantum dots. Superlattices Microstruct. 34 (3), 195-203
(2003)
6. Orlov, A.O., Amlani, I., Bernstein, G.H., Lent, C.S., Snider, G.L.: Realization of
a functional cell for quantum-dot cellular automata. Science 277 (5328), 928-930
(1997)
7. Amlani, I., Orlov, A.O., Toth, G., Bernstein, G.H., Lent, C.S., Snider, G.L.: Digital
logic gate using quantum-dot cellular automata. Science 284 (5412), 289-291 (1999)
8. Arima, V., Iurlo, M., Zoli, L., Kumar, S., Piacenza, M., Matino, F., Maruccio,
G., Rinaldi, R., Paolucci, F., et al.: Toward quantum-dot cellular automata units:
thiolated-carbazole linked bisferrocenes. Nanoscale 4 (3), 813-823 (2012)
9. Frost, S.E., Rodrigues, A.F., Janiszewski, A.W., Rausch, R.T., Kogge, P.M.: Mem-
ory in motion: a study of storage structures in QCA. In: Proceedings of the 1st
Workshop on Non-Silicon Computing, vol. 2, pp. 30-37 (2002)
10. Vankamamidi, V., Ottavi, M., Lombardi, F.: A line-based parallel memory for QCA
implementation. IEEE Trans. Nanotechnol. 4 , 690-698 (2005)
11. Walus, K., Mazur, M., Schulhof, G., Jullien, G.A.: Simple 4-bit processor based on
quantum-dot cellular automata (QCA). In: Proceedings of the 16th IEEE Inter-
national Conference on Application-Specific Systems, Architecture Processors, pp.
288-293 (2005)
12. Hanninen, I., Takala, J.: Pipelined array multiplier based on quantum-dot cellular
automata. In: Proceedings of the 18th European Conference on Circuit Theory
and Design, pp. 938-941 (2007)
13. Cho, H., Swartzlander Jr, E.E.: Adder and multiplier design in quantum-dot cel-
lular automata. IEEE Trans. Comput. 58 , 721-727 (2009)
14. Swartzlander Jr, E.E., Cho, H., Kong, I., Kim, S.W.: Computer arithmetic imple-
mented with QCA: a progress report. In: Conference Record of the 44th Asilomar
Conference on Signals, Systems and Computers, pp. 1392-1398 (2010)
15. Lu, L., Liu, W., O'Neill, M., Swartzlander Jr, E.E.: QCA systolic matrix multiplier.
In: Proceedins of the IEEE Annual Symposium on VLSI, pp. 149-154 (2010)
16. Niemier, M.T., Kogge, P.M.: Problems in designing with QCAs: layout = timing.
Int. J. Circuit Theory Appl. 29 (1), 49-62 (2001)
17. Zhang, R., Walus, K., Wang, W., Jullien, G.A.: A method of majority logic reduc-
tion for quantum cellular automata. IEEE Trans. Nanotechnol. 3 , 443-450 (2004)
18. Srivastava, S., Bhanja, S.: Hierarchical probabilistic macromodeling for QCA cir-
cuits. IEEE Trans. Comput. 56 , 174-190 (2007)
19. Choi, M., Patitz, Z., Jin, B., Tao, F., Park, N., Choi, M.: Designing layout-timing
independent quantum-dot cellular automata (QCA) circuits by global asynchrony.
J. Syst. Architect. 53 , 551-567 (2007)
20. Liu, W., Lu, L., O'Neill, M., Swartzlander Jr, E.E., Woods, R.: Design of quantum-
dot cellular automata circuits using cut-set retiming. IEEE Trans. Nanotechnol.
10 (5), 1150-1160 (2011)
21. Lu, L., Liu, W., O'Neill, M., Swartzlander Jr, E.E.: QCA systolic array design.
IEEE Trans. Comput. 62 , 548-560 (2013)
22. Timler, J., Lent, C.S.: Power gain and dissipation in quantum-dot cellular
automata. J. Appl. Phys. 91 (2), 823-830 (2002)
Search WWH ::




Custom Search