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written into during the execution of a logic function. In Fig.
6
,
X
21
,
X
23
,
X
24
and
X
26
are the output cells.
To summarize the execution of 2-input exclusive-OR,
x
1
⊕x
2
=
x
1
·x
ₓ
2
+
x
ₓ
1
·x
2
,
in relation to Fig.
6
, there are two AND operations and one OR operation. The
two ANDs are performed in the two AND gates with outputs
X
5
=
x
1
· x
ₓ
2
and
X
8
=
x
ₓ
1
· x
2
. Their outputs are ORed in the OR gate with
X
13
=
x
1
⊕ x
2
.The
differential output generator generates the complementary output bit. Finally,
X
24
and
X
26
stores the output and
X
21
and
X
23
stores the output complement.
Algorithm
1
compiles the steps till output generation in
X
13
.
Algorithm 1.
2
-Input
xor
execution
x
1
⊕
x
2
in STT-based logic-in-memory
architecture
1:
Inputs:
x
1
x
◦
1
,
x
2
,
x
◦
2
.
2:
Outputs:
S
a
=
S
b
=f(
x
1
,x
2
)=
x
1
⊕ x
2
.
3:
Write
X
1
=
x
◦
2
,
X
2
=
x
1
,
X
3
=
x
2
,
X
4
=
x
◦
1
.
4:
Clock
rows
r
2
and
r
6
.
5:
Release clock.
6:
X
5
,
X
6
,
X
7
settle to (
x
1
.
x
◦
2
), (
x
1
.
x
◦
2
)', (
x
1
.
x
◦
2
) resp.
7:
X
8
,
X
9
,
X
10
settle to (
x
◦
1
.
x
2
), (
x
◦
1
.
x
2
)', (
x
◦
1
.
x
2
) resp.
8:
Select
word line
WL
2
.
Clock
rows
r
3
and
r
5
.
9:
Release
clock.
10:
X
11
and
X
12
settle
to (
x
1
.
x
◦
2
), (
x
◦
1
.
x
2
) resp.
11:
Clock
row r
4
and then release the clock
12:
X
13
settles
to (
x
1
⊕x
2
).
4.3 Operational Details
As we mentioned earlier, one of the primary objectives behind replacing single
layer NML cells with multilayer MTJs was to take advantage of the low power
and on-chip write, clock and read mechanisms in MTJs. We will use the spin
transfer torque to write and clock the MTJs and their MR to read them. Advan-
tages of spin transfer torque over field induced write and clock are: (i) low power;
and (ii) high precision without stray field generation. The advantages of MR over
magnetic sensing include: (i) low read current; and (ii) on-chip read facility. To
start with, we will first see how to write into the MTJs and thereafter follow
with clocking and reading from them.
Writing.
To write into the input cells we first need to apply the appropriate
bias across their bit and source lines. With the help of their word lines, their
access transistors are next turned on. This provides a path for the current from
the bit to the source line or vice versa through the MTJ and its access transistor.
The direction of current again depends on the potential applied across the bit
and source lines. We will next see how the direction of electrons through the
MTJ determines whether a 0 or a 1 is written into it.
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