Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 149

enable testable D latch while the Fredkin gates labeled as 3 and 4 form the
negative enable testable D latch. In reversible logic fanout is not allowed so the
Fredkin gate labeled as 1 is used to copy the input signal D. The Fredkin gate
labeled as 6 works as the 2:1 MUX and transfer the output from one of these
testable latches (negative enable D latch or the positive enable D latch) that is in
the storage state (is holding its previous state) to the output Q. In the proposed
design of testable reversible DET flip-flop pC1 and pC2 are the control signals of
the testable positive enable D latch, while nC1 and nC2 are the control signals
of the testable negative enable D latch. Depending on the values of the pC1,
pC2, nC1 and nC2 the testable DET flip-flops works either in normal mode or
in the testing mode.
1. Normal Mode : The normal mode of the DET flip-flop is illustrated in Fig. 14 (a)
in which the pC1 = 0, pC2 = 1, nC1 = 0 and nC2 = 1. The pC1 = 0, pC2 = 1
helps in copying the output of the positive enable D latch thus avoiding the
fanout while the nC1 = 0 and nC2 = 1 helps in copying the output of the
negative enable D latch thus avoiding the fanout.
2. Test Mode : There will be two test modes:
(a) All 1s Test Vector : This mode is illustrated in Fig. 14 (c) in which control
signals will have values as pC1 = 1, pC2 = 1, nC1 = 1 and nC2 = 1. The
pC1 = 1 and pC2 = 1 help in breaking the feedback of the positive enable
D latch, while the nC1 = 1 and nC2 = 1 help in breaking the feedback
of the negative enable D latch. This makes the design testable by all 1s
test vector for any stuck-at-0 fault.
(b) All 0s Test Vector : This mode is illustrated in Fig. 14 (b) in which the
control signals will have values as pC1 = 0, pC2 = 0, nC1 = 0 and nC2 = 0.
The pC1 = 0 and pC2 = 0 help in breaking the feedback of the positive
enable D latch while the nC1 = 0 and nC2 = 0 help in breaking the feed-
back of the negative enable D latch. This makes the design testable by
all 0s test vector for any stuck-at-1 fault.
6 Design of Testable Reversible Complex Sequential
Circuits
The set of sequential building blocks proposed in this work can be used to build
complex sequential circuits that provide the capability of testing a sequential
circuit using two test vectors. The proposed sequential building blocks can be
used to implement various types of sequential circuits such as shifters, sequence
detectors, counters and systolic circuits etc. We have illustrated the method with
examples of design of reversible ring counter and reversible Johnson counter using
the proposed sequential building blocks.
6.1 Design of Testable Reversible Ring Counter
A testable reversible ring counter can be designed by cascading reversible master
slave D flip-flops with asynchronous set/reset capability in which the output of