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the last flip-flop is connected to the first flip-flop. The design of n bit testable
reversible ring counter is illustrated in Fig.
15
.In
normal working mode
, the ring
counter needs to be initialized by setting the first master-slave flip flop to 1,
while the remaining n-1 flip-flops need to be reset to 0. This will initialize the
counter to a state (10000
...
0)
n
. In Fig.
15
, this is performed as follows:
2
i
=
1 f
=0
0 f1
i
sc
1
i
and
sc
≤ i ≤
n
−
1
1 asynchronously sets
the first testable reversible flip-flop to 1, while the n-1 testable reversible D flip-
flops are asynchronously reset to 0. Once the counter is initialized, the values of
sc
The above values of
sc
1
i
and
sc
2
i
where 0
≤ i ≤ n −
1
i
and
sc
2
i
where 0
≤ i ≤ n −
1 are changed:
2
i
=
0
sc
1
i
and
sc
and
1 f0
≤ i ≤
n
−
1
Thus, in the proposed reversible n bit ring counter 1 bit is circulated so the
state repeats every n clock cycles. For example, in a four bit testable reversible
counter, the possible states for
Q
0
Q
1
Q
2
Q
3
will be 1000, 0100, 0010, and 0001.
The test mode of the reversible ring counter can be defined as follows:
(a)
All 1s Test Vector
: In this mode, all the inputs along with
sc
1
i
and
sc
2
i
1 are set to the value of 1 to detect any stuck-at-0 fault.
(b)
All 0s Test Vector
: In this mode, all the inputs along with
where 0
≤ i ≤ n −
sc
1
i
and
sc
2
i
where 0
≤ i ≤ n −
1 are reset to the value of 0 to detect any stuck-at-1
fault.
6.2 Design of Testable Reversible Johnson Counter
A testable reversible Johnson counter can be designed by cascading reversible
master slave D flip-flops with asynchronous set/reset capability in which the Q'
output of the last flip-flop instead of Q is connected to the first flip-flop. The
design of n bit testable reversible Fig.
16
.In
normal working mode
, the Johnson
counter needs to be initialized by reseting all n flip-flops. This will initialize the
counter to a state (00000
...
0)
n
. In Fig.
16
, this is performed as follows:
2
i
=
0
sc
1
i
and
sc
and
≤ i ≤
−
0 f0
n
1
The above values of
1 asynchronously reset the
n testable reversible D flip-flops to 0. Once the counter is initialized, the values
of
sc
1
i
and
sc
2
i
where 0
≤ i ≤ n −
sc
sc
≤ i ≤ n −
1
i
and
2
i
where 0
1 are changed:
2
i
=
0
sc
1
i
and
sc
and
1 f0
≤ i ≤
n
−
1
Thus, the proposed reversible n bit Johnson counter produces a couting sequence
so the state repeats every 2n clock cycles. For example, in a four bit testable
reversible Johnson counter, the possible states for
Q
0
Q
1
Q
2
Q
3
will be 0000, 1000,
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