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Table 2.
Overall comparisons
Existing method [
15
]
Proposed method
Reduction %
Level
Gate
Level
Gate
Level
Gate
b1
2
7
2
6
0.00
14.29
cm82a
3
7
3
6
0.00
14.29
majority
4
6
3
6
25.00
0.00
alu2
18
340
16
347
11.11
-2.06
x2
7
37
6
36
14.29
2.70
cm152a
6
21
6
17
0.00
19.05
cm85a
6
26
6
19
0.00
26.92
cm151a
7
23
7
20
0.00
13.04
cu
7
40
6
40
14.29
0.00
cm163a
7
38
7
32
0.00
15.79
cmb
4
28
4
26
0.00
7.14
pm1
6
35
6
32
0.00
8.57
vda
15
700
14
670
6.67
4.29
cm150a
9
46
6
37
33.33
19.57
mux
9
46
6
37
33.33
19.57
ttt2
11
145
10
144
9.09
0.69
i1
6
36
6
35
0.00
2.78
frg1
18
105
17
102
5.56
2.86
term1
11
106
10
89
9.09
16.04
k2
19
1301
19
1193
0.00
8.30
x1
11
264
11
253
0.00
4.17
example2
10
247
9
241
10.00
2.43
apex6
17
662
15
677
11.76
-2.27
frg2
14
582
13
600
7.14
-3.09
Average reductions
7.94
8.13
6
Conclusion
The approach to generate optimal majority expressions for all functions with four or
fewer variables is presented in this paper. In this approach, Nauty algorithm is used to
identify the standard functions and give the relationship between an arbitrary Boolean
function and its standard function. In order to convert a Boolean logic network, SIS
tool is used for preprocessing and decomposition. Using the standard functions, the
decomposed network is converted into a preliminary majority network. The redun-
dancy removal can then be applied to further simplify the result.
By summarizing these steps, an automated computer program is developed for
majority logic synthesis. Since the minority logic can be easily obtained by applying
De Morgan's Law to majority logic, this approach can also be used to build a minority
network. This synthesis method is integrated into SIS synthesis tool for better
usability.
Acknowledgements. This work was supported in part by National Science Foundation awards
0958298 and 0958355.
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