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been makes it more difficult for chip manufacturers to identify accelerators for vision
processors—different software implementations may want to see different interfaces
to the accelerator. A number of semiconductor manufacturers are now creating vision
accelerators. In addition, the semiconductor intellectual property (IP) providers are
developing vision accelerators that can be integrated into new designs. We should
expect to see a great deal of innovation in MPSoCs for vision over the next few years.
OpenVX (
http://www.khronos.org/openvx
)
is being developed as a standard API for
hardware accelerators for computer vision.
GPUs are widely used in desktop and laptop systems; smaller GPUs are now
common in cell phones. Some work has explored the use of GPUs for computer
vision. Fung et al. [
14
] developed the OpenVIDIA library for nVidia-based GPU-
based computer vision. Their library map the GPU's vertex processor, rasterizer,
and fragment processor onto various vision kernels. Their approach takes advantage
of fragment shader programs, which can be used to perform filtering on pixels; the
results of one filtering pass can be saved as a texture and used to perform another
filtering pass. Nagendra [
24
] developed an automotive vision system using GPUs.
The GPU implementations of the vision system, which used Viola and Jones object
detection as well as morphological filters, showed speedups of several times over a
3GHz CPU, but noted the significant power consumption of the GPUs used for the
experiment. Li et al. [
17
] implemented Haar transform-based face detection on an
Intel Sandy Bridge processor, which combines CPU cores and a GPU. Their results
showed an average speedup for the CPU-GPU combination of 3X over the CPU-only
implementation.
FPGAs provide powerful capabilities for the design of customized hardware plat-
forms for computer vision. Matai et al. [
20
] designed a complete face detection and
recognition system on an FPGA. The first stage of processing performed face detec-
tion using a design by Cho et al. [
4
]. That architecture is based on AdaBoost and com-
putes Haar classifiers to detect faces. Jacobsen et al. [
21
] designed an FPGA-based
system for accelerating online boosting for multi-target tracking. At each tracking
step, a region around the last known location is searched to find a new location and
new positive and negative training examples are selected. The classifier is used to
generate training data for the next step. This approach requires sequential passes
through the image data to first find the new location, then identify training exam-
ples. Classification is performed using Haar-like features that consist of between two
and six non-adjacent rectangles. The FPGA implementation could track 57 indepen-
dent targets at 30 frames/s. Gudis et al. [
11
] built FPGA-based vision systems based
on a crossbar-connected set of accelerators, a DRAM controller, and an ARM host
processor. The accelerators can be accessed via a C++ API.
Floating point is an important aspect of any embedded vision platform. Float-
ing point computation is used in higher level classifiers and also in some more
pixel-oriented algorithms such as optical flow. It is particularly important for FPGA-
based systems because floating point is one of the aspects that provides the biggest
cost/accuracy/performance trade-offs. IEEE compliant floating-point is not always
necessary and not always an asset. The ability to control the accuracy of number
representation is a basic consideration in platform design. The algorithm used to
