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area. Moreover, such a solution would also increase the overhead, in terms of recon-
figurable logic and memory controllers, required by the FPGA for handling multiple
external memory devices.
For the reasons outlined so far, in our design, we decided to avoid external mem-
ory devices at all. Although this choice enables to overcome some of the problems
previously outlined, it also means that we can rely only on the fast, yet small, memory
available inside the FPGA. As should be clear, this choice imposes very strong con-
straints on the algorithms that can be implemented on such a computing architecture.
Nevertheless, as we will show in the next sections, following specific algorithmic
methodologies, very effective results can be obtained adopting this simplified design
strategy.
5.5 Stereo Vision Algorithms Suited to the Constrained
Computing Architecture
A computing architecture similar to that outlined in the previous section poses signif-
icant constraints to the computational structure of the algorithms that can be imple-
mented. In fact, considering a representative case study of the Xilinx Spartan 6 FPGA
family [
44
], we can see that the overall block memory available is about 261 KB
for the Model 45 (and about 600KB for the most powerful device of this family, the
Model 150). In betweenmodels 45 and 150, there are two devices, 75 and 100, with an
amount of logic cells close to, respectively, 75,000 and 100,000 and with an amount
of block memory, respectively, of about 400KB and 600 KB. This means that, ignor-
ing other requirements, we would not even be able to store a stereo pair at WVGA
resolution (about 720 KB) in the most complex 150 device. This observation, plus
the limited overall reconfigurable logic available (about 43,000 and 147,000 logic
cells for the Model 45 and 150, respectively), dictates that
stream processing
[
2
]is
mandatory for our purposes. This technique consists of processing pixels as soon as
they are available from the imaging sensors, with minimal buffering requirements.
Of course, for the same reason, the resulting output cannot be entirely stored into
the FPGA and must be sent to the communications controller as soon as it is made
available by the processing pipeline. We also point out that other relevant constraints
are concerned with the overall reconfigurable logic available for processing (e.g.,
about 55,000 flip-flops for the Model 45 and 185,000 flip-flops for the Model 150)
and the maximum distributed RAM available (e.g., about 50KB for Model 45 and
about 17KB for Model 150). More details concerned with these devices are available
in [
44
].
In the next sections, we will consider some relevant stereo vision algorithms
potentially suited to this constrained target architecture. For this purpose, we will
adopt the classification proposed in [
31
], where algorithms are classified into two
major categories, local approaches and global approaches, making a further distinc-
tion when dealing with approaches not completely described by these two broad
categories.
