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In-Depth Information
Input Encoding
σ
Output Encoding
λ
(
q
)
State Encoding
q cs
q
0
00
q
1
01
q
2
10
q
3
11
Σ
uv
0000
0101
1010
1111
∈
∈
λ
(
q
)
Ψ
0
0
1
1
B
2
csuvc
∗
s
∗
000000
010000
100001
110001
000101
010101
100110
110110
001001
011001
101010
111010
001110
011110
101111
111111
δ
:
B
4
λ
:
B
2
→
B
c
∗
s
∗
s
000
011
100
111
→
Figure 3.14
Encodings for inputs, outputs, states, and the next-state and output functions of
the FSM adder.
c
c
∗
M
s
∗
s
M
g
Clock
p
u
v
Figure 3.15
A sequential circuit for the FSM that adds binary numbers.
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