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3.3.1 Binary Memory Devices
It is useful to fix ideas about memory units by designing one (a latch) from logic gates. We
use two latchs to create a flip-flop, the standard binary storage device. A collection of clocked
flip-flopsiscalleda
register
.Aclocked
latch
can be constructed from a few
AND
and
NOT
gates, as shown in Fig.
3.16
(a). The
NAND
gates (they compute
NOT
of
AND
) labeled
g
3
and
g
4
form the heart of the latch. Consider the inputs to
g
3
and
g
4
, the lines connected to the
outputs of
NAND
gates
g
1
and
g
2
. If one is set to 1 and the other reset to 0, after all signals
settle down,
ρ
and
ρ
∗
will assume complementary values (one will have value 1 and the other
will have value 0), regardless of their previous values. The gate with input 1 will assume output
0andviceversa.
Now if the outputs of
g
1
and
g
2
are both set to 1 and the values previously assumed by
ρ
and
ρ
∗
are complementary, these values will be retained due to the feedback between
g
3
and
g
4
, as the reader can verify. Since the outputs of
g
1
and
g
2
are both 1 when the clock input
(CLK in Fig.
3.16
) has value 0, the complementary outputs of
g
3
and
g
4
remain unchanged
when the clock is low. Since the outputs of a latch provide inputs to the logic-circuit portion
of a sequential circuit, it is important that the latch outputs remain constant when the clock
is low.
When the clock input is 1, the outputs of
g
1
and
g
2
are
S
and
R
, the Boolean
co
mplements
of
S
and
R
.If
S
and
R
are complementary, as is true for this latch since
R
=
S
,thisdevice
will store the value of
S
in
ρ
and its complement in
ρ
∗
.Thus,if
S
=
1, the latch is
set
to 1,
whereas if
R
=
1(and
S
=
0) it is
reset
to 0. This type of device is called a
D-type latch
.For
this reason we change the name of the external input to this memory device from
S
to
D
.
Because the output of the D-type latch shown in Fig.
3.16
(a) changes when the clock pulse
is high, it cannot be used as a stable input to a logic circuit that feeds this or another such flip-
flop. Adding another stage like the first but having the complementary value for the clock
pulse, as shown in Fig.
3.16
(b), causes the output of the second stage to change only while the
clock pulse is low. The output of the first stage does change when the clock pulse is high to
record the new value of the state. This is called a
master-slave edge-triggered flip-flop.
Other
types of flip-flop are described in texts on computer architecture.
D
=
S
g
3
ρ
ρ
g
1
g
2
CLK
CLK
ρ
∗
ρ
∗
g
4
R
(a)
(b)
Figure 3.16
(a) Design of a D-type latch from
NAND
gates. (b) A master-slave edge-triggered
D-type flip-flop.
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