Digital Signal Processing Reference
In-Depth Information
Input Signal,
x
(
k
)
Sampler &
ADC
x
(
t
)
DF
N
−bits
y
(
k
)
DCO
Output Pulses,
v
o
(
k
)
x
(
t
)
T
(1)
T
(2)
Time
t
(0)
t
(1)
t
(2)
x
(
k
)
x
( 1 )
x
( 2 )
x
( 3 )
v
o
(
t
)
Fig. D.14
Block diagram of the SDPLL with associated waveforms
The input x(t) is assumed to be a sinusoidal signal as follows:
x
ð
t
Þ¼
Asin
ð
xt
þ
h
o
Þþ
n
ð
t
Þ:
The phase difference equation for the 1st-order SDPLL is given by:
/
ð
k
þ
1
Þ¼
/
ð
k
Þ
K
2
sin
½
/
ð
k
Þþ
K
o
where K
o
¼
2p
ð
x
x
o
Þ=
x
o
and K
2
= x G
1
A. If we define K
1
= x
0
G
1
A, and
the frequency ratio W = x
o
/x, then we have K
2
= K
1
(x/x
o
) = K
1
/W.
The locking range is determined by the conditions:
K
1
[ 2p
j
1
W
j
and
K
1
\
p
ð
4
þ
4p
2
Þ
W
2
8p
2
W
þ
4p
2
:
It should be noted that extreme points in this range does not ensure locking for
all values of the initial phase error. The steady-state phase error is given by:
/
ss
¼
sin
1
ð
K
o
=
K
2
Þ:
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