DSP Lab Experiments - Digital Signal Processing: An Introduction with MATLAB and Applications - page 339

AWGN

Filter
matched
to "0"

Received data

Binary
data

Decision

Filter
matched
to "1"

Random
number
generator

Original data

Comparator

Error Counter

Fig. D.13 Flow chart of a binary communication system simulator

Task 2
Using the same approach (but one matched filter), simulate a binary
communication system with two antipodal signals. Find the probability of error
versus SNR. Compare with the theoretical result and with orthogonal signal
transmission.

Task 3

Simulate the above system without matched filters and compare with results in
Tasks 1 and 2 above.

Experiment # 8: Simulation of the Sinusoidal Digital
Phase-Locked Loop

Introduction

The sinusoidal DPLL (SDPLL) is an important system in signal processing and
communications. Like other PLLs, the SDPLL is a feedback system that arranges
its local frequency to be equal to the input frequency. It can be used for signal
detection, frequency tracking, and synchronization. Unless the incoming frequency
x is equal to the center frequency x o , the first-order SDPLL (which utilizes a
multiplication constant G 1 only in its filter) has always a non-zero steady-state
phase error, / ss . The 2nd-order SDPLL [which utilizes a first-order digital filter
H(z) = G 1 + G 2 /(1 - z -1 )] always locks on zero / ss . A block diagram of the
SDPLL is shown in Figure D.14 below. The sampler here operates as phase error
detector (PED).