Biomedical Engineering Reference
In-Depth Information
Pulse 1
Pulse 2
Pulse 10
Pulse
n
Pulse
n+1
Pulse
n+9
Pulse
51
Pulse
52
Pulse
60
Clock 1
Delay: 0 ns
Clock
m
Delay: 1.67*(
m-1
)ns
Clock 6
Delay: 8.35 ns
Fig. 6.3
Pulse detection using different sampling clocks
pulses for each clock are used to compensate for effects of any time jitters that
might occur in the received UWB pulse stream. Recorded pulse amplitudes are
compared against each other after all the clocks have finished sampling the pulse
stream (i.e. after a period of 60 consecutive pulses). The clock that records the
highest sampling value is chosen as the ADC sampling clock for data detection.
The ADC sampling clock determination procedure occurs within Sync portion of
the transmit packet structure. Operation of the above-mentioned sampling tech-
nique is shown in Figs.
6.3
and
6.4
.
IR-UWB pulse synchronization ensures that an optimum sampling clock is used
to sample the received UWB pulses. The clock synchronization procedure has to
operate within Sync portion of the transmit packet structure for accurate deter-
mination of the sampling clock. However, start of a super frame time slot might
not always be aligned with time of arrival of the packet structure. Hence, a pro-
cedure has to be developed in order to avoid the clock inaccuracies due to the
delay between start of the super frame time slot and packet arrival time. This is
achieved in the following manner.
The FPGA program defines an initial amplitude threshold value for detecting
the presence of a pulse. A pulse is considered present if the recorded pulse
amplitude by the ADC module exceeds the threshold value. The FPGA module
can detect amplitudes ranging from -1 to +1 V with a resolution of 5 mV.
Considering the fact that received pulses after the UWB front-end possess a
positive amplitude, 10 mV is chosen as the initial threshold level in the pulse
detection algorithm. Choosing the lowest possible threshold level for data detec-
tion eliminates the requirement for changing the threshold level according to
the distance between a sensor node and the coordinator node. Sync portion of the
transmit packet is followed by a 12 bit preamble sequence that is chosen to be
''010010110100''.
As described earlier, the ADC module samples 10 baseband pulses using each
clock (initial detections) in a sequential manner at the start of a super frame time
slot that has been allocated for the data transmission of a particular sensor node
(Fig.
6.5
a). This is carried out without prior knowledge of the position of Sync
portion within the received packet structure. The recorded pulse amplitudes for
each clock are compared against the initial threshold value in order to determine
