Biomedical Engineering Reference
In-Depth Information
Turn off UWB
transmitter
Start
Turn on UWB
transmitter and
transmit data
Turn on narrow
band receiver
Synchronize to
beacon on the
narrow band
channel
Wait for transmit
time slot
PPB adjustment
procedure
Transmit
initialization
request and starts a
timer
Synchronize to next
beacon
Yes
Initialization
acknowledged before
timeout ?
Scheduled data
acquisition from
sensors
Reception of BER
control messages?
Yes
No
No
Fig. 6.2
Operation of the sensor node control program
Stratix II FPGA development board [
9
] is used as the sampling and data pro-
cessing module of coordinator node. Stratix II FPGA development board has an
on-board ADC module that can sample the base band pulses at a sampling speed of
100 MHz and with a resolution of 12 bits per sample. Pulse detection and syn-
chronization algorithm is programmed into the FPGA module. Pulse detection
program in the FPGA operates a Digital Phase Locked Loop (DPLL) that gener-
ates six clocks with programmable delays with respect to a reference clock.
Function of the pulse synchronization algorithm implemented in the FPGA module
is to determine the ADC sampling clock that samples at the peak of received UWB
pulses. For example, consider a UWB system that operates at a 100 MHz PRF. In
this case, the UWB front-end will generate a base band pulse stream with pulses
that are 8 ns wide and 10 ns apart from each other. Six clocks having a delay of
1.67 ns (phase difference of 60) from each other and a clock frequency of
100 MHz are generated by the DPLL of the FPGA program. These clocks sample
the UWB pulse stream sequentially. Each clock samples 10 consecutive UWB
pulses and stores the recorded pulse amplitudes as a summation. Ten sample
