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(a)
DVM
(b)
TVM
(c)
DVM
(Correction)
(d)
TVM
(Correction)
Fig. 1.
The figure presents the basics Flexicache for DVM (Figure.1a) and TVM
(Figure.1b) for 8-bit partitions. Also, it presents examples for correctable and non-
correctable faults.
and Triple Version Mode (TVM). Flexicache divides each cache line into parity-
protected-partitions akin to many commercial L1 caches protected by single-bit
parity in block, word or byte granularity [21]. Figure 1 presents the design of
DVM and TVM for a hypothetical 8-bit partition. SVM, which is not presented
in the figure, provides reliability solely based on single bit interleaved parity. In
this study, Flexicache runs in SVM in the nominal voltage when the failure rate
is minimum in order to provide full cache capacity for the applications. Note
that instead of parity, a stronger code can also be utilized to provide a higher
reliability for mission critical applications.
Flexicache runs in DVM when the
V
dd
is medium-low and writes data to two
cache lines. Note that the circuit design allows writing/reading multiple lines
simultaneously (i.e. without increasing the access time) as we explain in the
following section. In a read, DVM compares two duplicated, parity-protected
partitions through the XORs to check if there is any fault. In case of the com-
plete match, Flexicache dispatches one of the partitions to the output buffer.
Otherwise, Flexicache calculates the parity of each partition and sends out the
partition which has the correct parity. DVM provides a backup copy for each
partition. For instance, when a particle strike effects several adjacent bits in a
line, the correct value is read from its replica without requiring any decode-and-
correct time. In order to avoid the possibility of a strike affecting both coupled
lines, Flexicache couples the lines with spatially distant locations. (e.g 0th and
63th lines.)
When the
V
dd
is near threshold, in order to tolerate the drastically increased
error rate, Flexicache runs in TVM by writing the data to three cache lines simul-
taneously. On a read, Flexicache uses bitwise majority voting to obtain the correct
data and calculates the parity of the data. Unless parity confirms that the result
is correct, Flexicache calculates the parities of three partitions and sends out the
correct partition. In TVM, the whole cache should be divided into three which is
not trivial for a cache having 2
n
lines. One solution can be manually connecting
lines by taking into account that the lines in the same group should be in distinct
positions (e.g. 0th, 42th and 84th lines for a 128-line cache). However, this con-
siderably increases the complexity of the address decoder. Instead, we add spare
lines to make the cache dividable into three. For instance, for a 128-line cache, we
