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In-Depth Information
Fig. 6.
hwloc
output describing the topology of the
jolly
multicore machine
For each of those architectures, we need to specify the instances in MultiBSP.
We proceed step by step for a better understanding of the MultiBSP formulation.
For
dell32
we start from bottom (cores) to upper levels and build the com-
ponents in tuples that share a memory space. The first tuple is made of a single
core at
level
0
. It does not shared any memory with any other component, so
its shared memory is 0 and both parameters
g
and
L
are zero by definition:
tuple
0
=
. Then, the basic 4 components in
level
0
share the L3 cache memory with a size of 5MB, building a new Multi-
BSP component level
1
. This new component is formally described by the tuple:
tuple
1
=
p
0
=1
,m
0
=0
,g
0
=0
,L
0
=0
. Finally, all eight components in level
1
share the RAM memory, with size of 64GB, building the next and last level,
level
2
, in a MultiBSP specification. This one is formally described by the tuple:
tuple
2
=
p
1
=4
,m
1
=5MB
,g
1
,L
1
.
We join all tuples using a sequence for a complete MultiBSP machine speci-
fication and discard the level
0
for our benchmark proposal, because the values
of
g
0
and
L
0
are known by definition. The architecture of instance #1 is then
described by Eq. 1.
p
2
=8
,m
2
=64GB
,g
2
,L
2
M
1
=[
p
1
=4
,m
1
=5MB
,g
1
,L
1
,
p
2
=8
,m
2
=64GB
,g
2
,L
2
]
(1)
Using the same procedure, we build the MultiBSP specification for instance
#2,
jolly
. Again, level
0
is described by
tuple
0
=
.
It is the same in all machines, except for cores that use the hyperthreading
technology (in that case, an extra level is need to specify physical threads). Then,
there are two components sharing the L2 cache, with a size of 2 MB. The level
1
is described by
tuple
1
=
p
0
=1
,m
0
=0
,g
0
=0
,L
0
=0
The components at level
1
are grouped by sharing four L3 cache memories, with a size of 6MB, building
the level
2
, as defined by
tuple
2
=
p
1
=2
,m
1
=2MB
,g
1
,L
1
p
2
=4
,m
2
=6MB
,g
2
,L
2
. In the last level
