Biomedical Engineering Reference
In-Depth Information
microcontroller consumes 1 µA of power at 1 MHz and linearly increases power to its maximum at
8 MHz. In addition, there are other power modes that allow it to use infinitesimally small amounts
of power with voltage ranges from 1.8 to 3.6 V. For the NSP, we use 3.3 V to supply the microcon-
troller. Furthermore, the microcontroller has 48 KB of flash RAM that can store data when power
is off and 10 KB when the power is on. Combined with a 12A/D-D/A and multiple asynchronous/
synchronous serial ports and SPI/I2C ports, this microcontroller is very well endowed for such a
small package (10 × 10 mm).
Handling the wireless protocol is one of the main functions this coprocessor is in charge of. It
provides the DSP communication transparency when sending and receiving wireless data. Underneath
this transparency the multifunctional component (MSP) is controlling the flow and control of the wire-
less chip. We also use the MSP as a boot loader for the DSP by using its serial port for booting. To boot
the DSP serially, we store the DSP program in the flash because the MSP has 48 KB of flash. Essen-
tially, by using the MSP to boot the DSP, we trade one single functioned component for an MSP that
is lower power. In terms of expandability, the MSP is fast enough (8 million instructions per second)
to handle preprocessing of the neural data for the prediction models running on the DSP. Through a
serial port or a digital IO (connected to the flex and interconnects), we can also expand the system to in-
clude USB communications for the uploading or downloading of data in real time (from multiple paths
MSP/DSP/analog module). We can also use these ports to create a test bed for debugging the system or
testing future analog modules. Finally, similar to the wireless chips, we have the ability to scale the NSP
system and add multiple coprocessors because they are very low power and small, yet highly functional.
Reconfigurability.
1) Complex Programmable Logic Device (CPLD). By using an Altera C3000,
the NSP is able to expand and accommodate future needs. There are options for using on-board clocks
as well as off-board and even clocks from the analog module. This makes for a very flexible system
for future analog modules that require or provide clock signals. Communication is also reconfigurable
because it is critical between the components on-board and modules off board. This includes the serial
ports from the DSP and MSP, and the parallel data bus from both processors. Through the CPLD
we have the ability to use a USB connection and other serial ports. These in turn can be redirected to
the DSP or the MSP. The NSP even has the ability to redirect the wireless connection directly to the
external IO for debugging and support. Essentially, the CPLD is very useful for debugging the system
and add future features that may become required. It has access to all the connectors and components.
Because it is reprogrammable through very high speed integrated circuit hardware (VHDL), it makes
for a very versatile hardware component.
2) Connector Interface. To complement the CPLD and allow for functionality of unknown
future needs it is necessary to provide as much connectivity between the internal components to the
