Biomedical Engineering Reference
In-Depth Information
mathematical operations in a single cycle. With support for both assembler and C/C++, code for the
DSP can be optimized at low and high programming levels for additional speed support. Even at
200 MFLOPS, the C33 is also well suited to low power needs because it uses less than 200 mW. It
achieves such power savings due in part to its 1.8-V core and other power-saving measures built into
the processor. Using adjustable clock speeds, the DSP can exchange processing speed for lower power
consumption. This may be desirable because some BMI experiments may require increased battery life
in exchange for less computational speed (i.e., less neural data). Finally, the C33 is able to fulfill other
expandability requirements of the system. First, it supports a large address space by providing a 24-bit
address bus to read/write 16 million different locations. This address space is used to map the different
hardware components of the system and future hardware interfaces. It includes a 32-bit parallel data
bus and serial port for multiple communication methods and hardware multiplexing. This processor
can also provide expansion because it has four hardware interrupts, two 32-bit timers, and a direct
memory access controller that can be used for future requirements or hardware interfaces.
wireless Communication.
As with the PICO system, the wireless connection is the second most
important hardware module in the NSP. This module, similar to the processor, has the ability to
define the size and power consumption of the full system. Early on, we determined that 802.11B
was the most convenient protocol for our group and collaborators [
18
]; unfortunately, it required a
PCMCIA card that was very large and consumed the majority of the power from the system.
Because the digital module does not need a lot of bandwidth to transmit 100-msec trajectory co-
ordinates (20 bytes), and the possible connection to the analog frontend if wireless uses at most
500 kbits/sec, we sacrifice the bandwidth of the PCMCIA card and 802.11Bs universal protocol
for a tiny low power 2.4-GHz wireless solution. This wireless chip (also used in the PICO), Nordic
nRF2401, is a single chip transceiver capable of 1 Mbp/sec at 10.5 mA (peak). It also has the abil-
ity to reduce its power further to 0.8 mA if we use ShockBurst mode or any variant in between.
Compared to the 100- to 300-mA PCMCIA card (depending on throughput), this is a significant
savings in power. In addition, the package size of the Nordic chip is only 5 × 5 mm compared to the
4.5 × 2.25-in. PCMCIA card used in the previous design. Although there is an additional antenna,
it is only a 6.5 × 2.2 mm surface mount SMD, still making the Nordic chip a significant savings in
size and power.
MSP Coprocessor/Boot-loader.
The NSP contains a coprocessor to alleviate the computa-
tional strain on the DSP. In turn, this coprocessor supports the current peripheral functions of the
digital module and any future functions. Consequently, this allows the DSP to solely concentrate
on the algorithms for neural-to-trajectory mappings. We chose the MSP430F1611x to serve as the
coprocessor because it is a very low power yet highly functional microcontroller. This 16-bit RISC
