The Architecture of Electronic Data Carriers - RFID: Fundamentals and Applications in Contactless Smart Cards and Identification - page 271

The data memory, which comprises a ROM for permanent data such as serial num-
bers, and EEPROM or FRAM is connected to the address and security logic via the
address and data bus inside the chip.
The system clock required for sequence control and system synchronisation is
derived from the HF field by the HF interface and supplied to the address and secu-
rity logic module. The state-dependent control of all procedures is performed by a
state machine ('hard-wired software'). The complexity that can be achieved using
state machines comfortably equals the performance of microprocessors (high end
transponders). However the 'programme sequence' of these machines is determined
by the chip design. The functionality can only be changed or modified by modifying
the chip design and this type of arrangement is thus only of interest for very large
production runs.

10.1.2.1 Statemachine

A state machine (also switching device, Mealy machine) is an arrangement used for
executing logic operations, which also has the capability of storing variable states
(Figure 10.8). The output variable Y depends upon both the input variable X and what
has gone before, which is represented by the switching state of flip-flops (Tietze and
Schenk, 1985).
The state machine therefore passes through different states, which can be clearly
represented in a state diagram (Figure 10.9). Each possible state S Z of the system is
represented by a circle. The transition from this state into another is represented by
an arrow. The arrow caption indicates the conditions that the transition takes place
under. An arrow with no caption indicates an unspecified transition (power on → S 1 ).
The current new state S Z (t + 1 ) is determined primarily by the old state S Z (t) and,
secondly, by the input variable x i .
The order in which the states occur may be influenced by the input variable x .If
the system is in state S Z and the transition conditions that could cause it to leave this
state are not fulfilled, the system remains in this state.

Input
variable X

Output
variable Y

Switching
network
(PROM)

State
variables
(flip-flop • n)

Z t + 1 (t, X)

Z t

Φ

Figure 10.8 Block diagram of a state machine, consisting of the state memory and a backcou-
pled switching network