The Architecture of Electronic Data Carriers - RFID: Fundamentals and Applications in Contactless Smart Cards and Identification - page 268

Table 10.1 The clock frequencies required in the HF interface are
generated by the binary division of the 13.56MHz carrier signal

Splitter N Frequency Use

1/28 485 kHz φ 2 of the FSK subcarrier

1/32 423 kHz φ 1 of the FSK subcarrier, plus

ASK subcarrier

1/512 26.48 kHz Bit clock signal for high baud rate

1/2048 6.62 kHz Bit clock signal for slow baud rate

between ASK and FSK modulation. The modulated subcarrier signal is now transferred
to switch S , so that the modulation resistor of the load modulator can be switched on
and off in time with the subcarrier frequency.

10.1.1.2 Example circuit -HF interface for ISO14443
transponder

The circuit in Figure 10.5 provides a further example of the layout of a HF interface.
This was originally a simulator for contactless smart cards in accordance with ISO
14443, which can be used to simulate the data transmission from the smart card to a
reader by load modulation. The circuit was taken from a proposal by Motorola for a
contactless smart card in ISO 10373-6 (Baddeley and Ruiz, 1998).
A complete layout is available for the duplication of this test card (see Section
14.4.1). The circuit is built upon an FR4 printed circuit board. The transponder coil
is realised in the form of a large area conductor loop with four windings of a printed
conductor. The dimensions of the transponder coil correspond with the ratios in a real
smart card.
The transponder resonant circuit of the test card is made up of the transponder
coil L 1 and the trimming capacitor CV 1 . The resonant frequency of the transponder
resonant circuit should be tuned to the transmission frequency of the reader, 13.56MHz
(compare Section 4.1.11.2). The HF voltage present at the transponder resonant circuit
is rectified in the bridge rectifier D 1 - D 4 and maintained at approximately 3 V by the
zener diode D 6 for the power supply to the test card.
The binary divider U 1 derives the required system clocks of 847.5 kHz (subcar-
rier, divider 1/16) and 105.93 kHz (baud rate, divider 1/128) from the carrier fre-
quency 13.56MHz.
The circuit made up of U 2 and U 3 is used for the ASK or BPSK modulation of the
subcarrier signal (847.5 kHz) with the Manchester or NRZ coded data stream (jumper
1-4). In addition to the simple infinite bit sequences 1111 and 1010, the supply of an
external data stream (jumper 10) is also possible. The test smart card thus supports both
procedures for data transfer between smart card and reader defined in ISO 14443-2.
Either a capacitive ( C 4 , C 5 ) or an ohmic ( R 9 ) load modulation can be selected. The
'open collector' driver U 4 serves as the output stage ('switch') for the load modulator.
The demodulation of a data stream transmitted from the reader is not provided in this
circuit. However, a very simple extension of the circuit (see Figure 10.6) facilitates
the demodulation of at least a 100% ASK modulated signal. This requires only an