Digital Signal Processing Reference
In-Depth Information
To calculate the CRC value for the entire data block, the CRC value from the preceding
data byte is used as the starting value for the subsequent data byte.
If the CRC value that has just been calculated is appended to the end of the data
block and a new CRC calculation performed, then the new CRC value obtained is zero.
This particular feature of the CRC algorithm is exploited to detect errors in serial data
transmission.
When a data block is transmitted, the CRC value of the data is calculated within
the transmitter and this value is appended to the end of the data block and transmitted
with it. The CRC value of the received data, including the appended CRC byte, is
calculated in the receiver. The result is always zero, unless there are transmission
errors in the received block. Checking for zero is a very easy method of analysing the
CRC checksum and avoids the costly process of comparing checksums. However, it is
necessary to ensure that both CRC calculations start from the same initial value. See
Figure 7.5.
The great advantage of CRCs is the reliability of error recognition that is achieved
in a small number of operations even where multiple errors are present (Rankl and
Effing,1996). A 16-bit CRC is suitable for checking the data integrity of data blocks up
to 4 Kbytes in length — above this size performance falls dramatically. The data blocks
transmitted in RFID systems are considerably shorter than 4 Kbytes, which means that
12- and 8-bit CRCs can also be used in addition to 16-bit CRCs.
Examples of different generator polynomials:
x
8
+
x
4
+
x
3
+
x
2
CRC-8 generator polynomial:
+
1
x
16
+
x
15
+
x
2
CRC-16/disk controller generator polynomial:
+
1
x
16
+
x
12
+
x
5
CRC-16/CCITT generator polynomial:
+
1
Transmitted data
CRC
46
72
61
6E
7A
E5
80
00
00
46
72
61
6E
7A
E5
80
Received data
CRC check
Figure 7.5
If the CRC is appended to the transmitted data a repeated CRC calculation of all
received data yields the checksum 0000h. This facilitates the rapid checking of data integrity
without knowing the CRC total
0
LSB
MSB
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Figure 7.6
Operating principle for the generation of a CRC-16/CCITT by shift registers
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