Image Processing Reference
In-Depth Information
Figure 9.15
Histogram resources utilization.
the resources taken up in the target FPGA and their utilization in the implemented
designs.
The greatest difference between the resulting designs, in terms of resources, is
in terms of the number of slices used. The partial-sort algorithm uses up to 87% of
the whole FPGA while the histogram implementation barely uses 9%. Figure 9.17
shows the Floorplanner views of both designs. This is the allocation of resources on
the device. It can be seen that the histogram uses far fewer resources.
These results are to be expected because the partial-sort algorithm only uses
logic to perform the calculations. Consequently, it suffers from place and route
problems. However, the histogram relies heavily on the use of memory blocks
available on the FPGA.
This would not be the case if the designs were aimed at an ASIC. The equiva-
lent gate count parameter in Figs. 9.15 and 9.16 indicates the approximate size of an
ASIC to implement the design. For the partial-sort, only 278,412 gates are required,
whereas the histogram requires 990,385. This huge difference is due to the large
equivalent gate size for the memory blocks used in the local histogram approach.
These parameters show that the histogram implementation is better-suited for
the FPGA but that the partial-sort algorithm would be expected to outperform the
histogram design in a hypothetical ASIC implementation.
In terms of throughput, the partial-sort is more efficient, processing each frame
in less than half the clock cycles. The FPGA performance tests show that the aver-
age processing time per frame is 0.0029 seconds for the partial-sort algorithm and
0.0070 seconds for the histogram.
