Image Processing Reference
In-Depth Information
512 Mb of RAM. There are two situations where hardware implementation may be
of significant benefit: for the filter training process and for real-time implementa-
tion of spatio-temporal filters.
During training, the filtering process must be repeated many times and the
quality criterion evaluated. In the example given, the first 35 iterations were com-
pleted in 30 minutes and 500 iterations took four hours and 20 minutes. Each iter-
ation of the GA therefore took just under one minute to complete. This process
could therefore benefit from hardware implementation. However, the training is
usually carried out offline, so the longer processing times are not usually a prob-
lem.
A more challenging task is the implementation of a real-time spatio-temporal
filter. This is because it must process a window that not only extends over 5 × 5 pix-
els, but also spans 3 frames. This requires that at least 75 pixels (depending on the
repetition parameter) must be sorted in real time to find the
r
th largest or smallest
value. If the processing involves multiple operations such as
soft erode
followed by
soft dilate
, then the intermediate values must be stored and processed again.
In order to test the viability of processing video streams in real time, two differ-
ent strategies were implemented on a Xilinx-Virtex-II-based field-programmable
gate array (FPGA).
11,12
The strategies differed only in the way they carried out the
sorting process. The images were in approximate CIF format (360 × 280) and full
24-bit RGB color. In this case, the separate RBG color plans were filtered sepa-
rately and recombined. This was found to give perceptually pleasing results,
though this is contrary to popular wisdom. A comprehensive guide to the process-
ing of color images is given in Sangwine.
13
The two strategies implemented were called the partial-sort algorithm and the
histogram algorithm.
14,15
In the partial-sort algorithm, a traditional pairwise swapping approach
16
was
used to obtain the maximum value in the set. This maximum value was then re-
moved and the process repeated to find the 2
nd
largest value, and so on until the
r
th
rank was obtained. For low ranks it was simpler to start at the bottom and work up.
The histogram algorithm, on the other hand, exploits the fact that the image
data lies within a limited dynamic range. It is implemented by mapping the pixel
values into a traditional histogram. The process of creating the histogram implicitly
carries out a sorting operation in itself. The
r
th-ranked value is then simply deter-
mined by beginning at one end and counting the pixels in the histogram until the de-
sired rank is obtained. The histogram approach is heavily dependent on the
on-board memory used to accumulate the histogram whereas the partial-sort works
purely with raw logic.
Both designs were synthesized using the Synplify 7.2 tool.
17
The target fre-
quency used to set up the synthesis stage was 80 MHz. The partial-sort algorithm
just managed to achieve this, whereas the histogram design was able to operate up
to 110 MHz.
Figures 9.15 and 9.16 show the output of the MAP tool of the Xilinx ISE v6.1
software for the histogram and partial sorting algorithms, respectively. They show
