Digital Signal Processing Reference
In-Depth Information
Clock status
indicator
Figure 21.2. Clock sense indication.
21.3 Check That Clocks and Resets are
Working
Incorrectly functioning clocks or resets are a common cause of
design failures, which should be ruled out early in the debug
process
even experienced engineers have wasted hours of time
debugging apparently failed systems where the clock has been
disabled or the wire supplying the clock signal from a test device
to the board has been knocked off.
Other causes of clock failures include Phase locked loops
which are unable to lock because their input signal has too much
jitter or is outside the acceptable range of input frequencies.
Reset signals can also become stuck
e
either holding part of
the design in reset permanently or never resetting it. If a design is
not reset then it does not start in a consistent state, and may get
into a state that its designer did not intend. Sometimes a design
will get out of these unusual states and sometimes it will become
stuck.
FPGA designs with reset faults sometimes work because the
configuration logic within the FPGA sets most registers to their
defined reset state at the end of configuration.
Most debug tools, for example the Altera SystemConsole
tool, provide ways to check that clocks are running and resets
are behaving correctly. In SystemConsole the explorer window
shows a green clock badge on nodes that have a running clock
and a red clock badge (with associated tooltip) on nodes which
can sense the clock but do not detect it running.
It also provides the jtag_debug service to give scripted access
to the clock sensing hardware. The TCL below shows an example
of its use:
set jd [lindex [get_service_paths jtag_debug] 0]
open_service jtag_debug $jd
puts
e
“
Clock running: [jtag_debug_sense_clock $jd]
”
puts
“
Reset status: [jtag_debug_sample_reset $jd]
”
