Digital Signal Processing Reference
In-Depth Information
larger than the hold time, so the first equation is the harder to
satisfy. This equation can always be satisfied by decreasing the
clock frequency (increasing the clock period) but this is usually
unsatisfactory, especially for video designs where a minimum
clock frequency is required to process all the pixels in a frame.
Another method is to buy a chip at a faster speed grade.
Unfortunately this has cost implications or is not possible
because previously shipped products need to be upgraded.
Other methods of making a design meet timing include:
inserting buffer registers to reduce the length of combinational
paths; changing the layout to place critical registers closer to each
other; and reducing the fan out of signals (which can increase
switching speed and make the layout simpler).
If the timing tool reports hold-time violations that reducing
the clock speed will not fix, design changes are required. Refer to
FPGA Design: Best Practices for Team based design (Simpson)
ISBN
13: 978-1441963383.
If you are using library components to create your design then
the component designer will have already considered these issues
and may have included parameters which help their component
meet timing (usually in exchange for an increase in size or latency).
Many libraries include components called
pipeline bridges
(or
similar names) which can be used to easily insert buffer registers
into all the signals of a bus without affecting its behavior.
e
21.2 The SystemConsole Debugger
As we will use SystemConsole as an example of a tool running
on a debug host we will now provide a basic introduction.
Debug tools usually refer to the system being debugged as the
target
the systemwhich you use to debug the target is the
debug
host
. The host will be connected to the target via one or more
debug cables (nowadays these are normally JTAG, USB or
Ethernet
e
though debugging over other media is possible).
To enable debugging, the system designer places
debug agents
within the target system. These agents are sometimes packaged
within other components
e
for example, most processor
components now contain a debug module
e
or they can be
e
explicitly instantiated by the system designer.
Those debug agents that use a JTAG interface to communicate
with the host are automatically connected to the JTAG pins on the
device by the Quartus software. In the current Altera software,
debug agents using other cables (USB and Ethernet) must be
explicitly connected to the pins on the device.
