Digital Signal Processing Reference
In-Depth Information
20
MEMORY CONSIDERATIONS
WHEN BUILDING A VIDEO
PROCESSING DESIGN
CHAPTER OUTLINE
20.1 The Frame Buffer 191
20.2 Calculating External Memory Bandwidth Required
194
20.3 Calculating On-Chip Memory
199
20.4 Conclusion
200
is
significantly compute and memory intensive. When building an
HD video-processing signal chain in hardware, whether in ASIC
or FPGA, you must be aware of both the computation resources
and the internal and external memory resources that will be
needed.
This chapter will use simple examples of designs to explain
how to calculate memory resources. First we will look at external
memory bandwidth since in any HD video processing system the
pixels required for calculation cannot be stored on-chip. External
DDR memory is also a very important consideration. To ascertain
this bandwidth we will look at the frame-buffer function and the
motion-adaptive deinterlacing function.
We will then assess internal on-chip memory requirements
Video processing
especially HD video processing
e
e
e
especially for functions like the video scaler which processes lines
of video within a given frame.
20.1 The Frame Buffer
This function is widely used in a range of video-processing
signal chains. Frame buffers do exactly what the name suggests
e
it buffers video frames, not just lines, in an external DDRmemory.
Buffering is frequently required to match the data rates and
thus reduce video burstiness. Frame buffers take in a frame of
