Digital Signal Processing Reference
In-Depth Information
Template x origin
Template x
Memory
x
Multiplier
Adder
Memory
Address
Calculation
Addr = x + Ly
Template y origin
Template Scale
y
Multiplier
Adder
Template y
Memory
Address
Image
Memory
Pixel Data
Contour Integral
Accumulator
Figure 19.6. Block diagram of
a contour integral engine.
19.2.2 FPGA Implementation
Figure 19.6
shows a block diagram of a system designed to
perform a contour integral. The base template is stored as x and y
coordinates in two separate memories. Template expansion is
performed by multiplying the template coordinates by a scaling
factor, and the scaled template coordinates are fed to an adder.
Here the x and y offset coordinates are added to generate an (x, y)
coordinate reference within the image frame. This (x, y) reference
must be manipulated to create a linear address within the image
frame store. Assuming image rows are stored in contiguous
memory blocks, this would involve multiplying y by the image
line width and adding x. The generated address can be used to
retrieve the pixel data from memory, and the data fed to an
accumulator which will sum all the pixel data for the contour
defined by the scaled and shifted template.
By pipelining the operations, it is possible for an FPGA to
perform all the operations in parallel, so that memory-access
speed becomes the performance limitation. Depending on the
image size, it may be possible to store the image in internal FPGA
RAM. If this is possible then not only can the memory operate at
higher speed, but the dual-port feature of the internal RAM can be
used so that two of these contour integral engines can be
executed in parallel.
