SECTION 14.2: MEMORY ADDRESS DECODING
In this section we discuss address decoding. The CPU provides the address of the data desired, but it is the job of the decoding circuitry to locate the selected memory block. To explore the concept of decoding circuitry, we look at various methods used in decoding the addresses. In this discussion we use SRAM or ROM for the sake of simplicity.
Memory chips have one or more pins called CS (chip select), which must be activated for the memory’s contents to be accessed. Sometimes the chip select is also referred to as chip enable (CE). In connecting a memory chip to the CPU, note the following points.
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The data bus of the CPU is connected directly to the data pins of the memory
chip.
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Control signals RD (read) and WR (memory write) from the CPU are con
nected to’the OE (output enable) and WE (write enable) pins of the memory
chip, respectively.
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In the case of the address buses, while the lower bits of the addresses from the
CPU go directly to the memory chip address pins, the upper ones are used to
activate the CS pin of the memory chip. It is the CS pin that along with
RD/WR allows the flow of data in or out of the memory chip. No data can be
written into or read from the memory chip unless CS is activated.
As can be seen from the data sheets of SRAM and ROM, the CS input of a memory chip is normally active low and is activated by the output of the memory decoder. Normally memories are divided into blocks, and the output of the decoder selects a given memory block. There are three ways to generate a memory block selector: (a) using simple logic gates, (b) using the 74LS138, or (c) using programmable logics. Each method is described below with some examples.
Figure 14-4. Logic Gate as Decoder
Figure 14-5. 74LS138 Decoder
(Reprinted by permission of Texas Instruments, Copyright Texas Instruments, 1988)
Simple logic gate address decoder
The simplest method of constructing decoding circuitry is the use of a NAND gate. The output of a NAND gate is active low, and the CS pin is also active low, which makes them a perfect match. In cases where the CS input is active high, an AND gate must be used. Using a combination of NAND gates and inverters, one can decode any address range. An example of this is shown in Figure 14-4, which shows that A15 – A12 must be 0011 in order to select the chip. This results in the assignment of addresses 3000H to 3FFFH to this memory chip.
Using the 74LS138 3-8 decoder
This is one of the most widely used address decoders. The 3 inputs A, B,’and C generate 8 active-low outputs YO – Y7. See Figure 14-5. Each Y output is connected to CS of a memory chip, allowing control of 8 memory blocks by a single 74LS138. In the 74LS138, where A, B, and C select which output is activated, there are three additional inputs, G2A, G2B, and Gl. G2A and G2B are both active low, and Gl is active
Figure 14-6. 74LS138 as Decoder
Example 14-6
high. If any one of the inputs Gl, G2A, or G2B is not connected to an address signal (sometimes they are connected to a control signal), they must be activated permanently either by Vcc or ground, depending on the activation level. Example 14-6 shows the design and the address range calculation for the 74LS138 decoder.
Using programmable logic as an address decoder
Other widely used decoders are programmable logic chips such as PAL and GAL chips. One disadvantage of these chips is that they require PAL/GAL software and a burner (programmer), whereas the 74LS138 needs neither of these. The advantage of these chips is that they can be programmed for any combination of address ranges, and so are much more versatile. This plus the fact that PALs and GALs have 10 or more inputs (in contrast to 6 in the 74138) means that they can accommodate more address inputs.
