So far all our discussion about memory space has involved program code. We have stated that the program counter in the 8051 is 16-bit and therefore can access up to 64K bytes of program code. In Chapter 6, we showed how to place data in the code space and used the instruction “MOVC A, OA+DPTR” to get the data. The MOVC instruction, where C stands for code, indicates that data is located in the code space of the 8051. In the 8051 family there is also a separate data memory space. In this section we describe the data memory space of the 8051 and show how to access it in Assembly.
Data memory space

Figure 14-13. 8051 Connection to External Data ROM

In addition to its code space, the 8051 family also has 64K. bytes of data memory space. In other words, the 8051 has 128K bytes of address space of which 64K bytes are set aside for program code and the other 64K bytes are set aside for data. Program space is accessed using the program counter (PC) to locate and fetch instructions, but the data memory space is accessed using the DPTR register and an instruction called MOVX, where X stands for external (meaning that the data memory space must be implemented externally).

External ROM for data
To connect the 8031/51 to external ROM containing data, we use RD (pin P3.7). See Figure 14-13. Notice the role of signals PSEN and RD. For the ROM containing the program code, PSEN is used to fetch the code. For the ROM containing data, the RD signal is used to fetch the data. To access the external data memory space we must use the instruction MOVX as described next.
MOVX instruction
MOVX is a widely used instruction allowing access to external data memory space. This is true regardless of which member of the 8051 family is used. To bring externally stored data into the CPU, we use the instruction “MOVX A, @DPTR”. This instruction will read the byte of data pointed to by register DPTR and store it in the accumulator. In applications where a large data space is needed, the look-up table method is widely used. See Examples 14-9 and 14-10 for the use of MOVX.
Example 14-9
An external ROM uses the 8051 data space to store the look-up table (starting at 1000H) for DAC data. Write a program to read 30 bytes of these data and send them to PI.

Example 14-10
External data ROM has a look-up table for the squares of numbers 0-9. Since the internal RAM of the 8031/51 has a shorter access time, write a program to copy the table elements into internal RAM starting at address 30H. The look-up table address starts at address 0 of external ROM.

Contrast Example 14-10 with Example 5-8 from Chapter 5. In that example the table elements are stored in the program code space of the 8051 and we used the instruction “MOVC” to access each element. Although both “MOVC A, ©A+DPTR” and “MOVX A, @DPTR” look very similar, one is used to get data in Tthe code space and the other is used to get data in the data space of the microcontroller.
Example 14-11
Show the design of an 8031-based system with 8K bytes of program ROM and 8K bytes of data ROM.
Figure 14-14 shows the design. Notice the role of PSEN and RD in each ROM. For program ROM, PSEN is used to activate both OE and CE. For data ROM, we use RD to activate OE, while CE is activated by a simple decoder.

Figure 14-14. 8031 Connection to External Data ROM and External Program ROM
From the discussion so far, we conclude that while we can use internal RAM and registers located inside the CPU for storage of data, any additional memory space for read/write data must be implemented externally. This is discussed further next.
External data RAM
To connect the 8051 to an external SRAM, we must use both RD (P3.7) and WR (P3.6). This is shown in Figure 14-15.

MOVX instruction for external RAM data
In writing data to external data RAM, we use the instruction “MOVX @DPTR, A” where the contents of register A are written to external RAM whose address is pointed to by the DPTR register. This has many applications, especially where we are collecting a large number of bytes of data. In such applications, as we collect data we must store them in NV-RAM so that when power is lost we do not lose the data. See Example 14-12 and Figure 14-15.
Example 14-12
  1. Write a program to read 200 bytes of data from PI and save the data in external
    RAM starting at RAM location 5000H.
  1. What is the address space allocated to data RAM in Figure 14-15?

Figure 14-15. 8051 Connection to External Data RAM

A single external ROM for code and data

Assume that we have an 8031 -based system connected to a single 64Kx8 (27512) external ROM chip. This single external ROM chip is used for both program code and data storage. For example, the space 0000 – 7FFFH is allocated to program code, and address space DOOOH – FFFFH is set aside for data. In accessing the data, we use the MOVX instruction. How do we connect the PSEN and RD signals to such a ROM? Notice in the previous discussion that PSEN is used to access the external code space and the RD signal is used to access the external data space. To allow a single ROM chip to provide both program code space and data space, we use an AND gate to signal the OE pin of the ROM chip as shown in Figure 14-16.

Figure 14-16. A Single ROM for Both Program and Data
8031 system with ROM and RAM
There are times that we need program ROM, data ROM, and data RAM in a system. This is shown in Example 14-13.
Example 14-13
Assume that we need an 8031 system with 16KB of program space, 16KB of data ROM starting at 0000, and 16K of NV-RAM starting at 8000H. Show the design using a 74LS138 for the address decoder.
The solution is diagrammed in Figure 14-17. Notice that there is no need for a decoder for program ROM, but we need a 74LS138 decoder for data ROM and RAM. Also notice that Gl = Vcc, G2A = GND, G2B = GND, and the C input of the 74LS138 is also
grounded since we use YO – Y3 only.

Figure 14-17. 8031 Connection to External Program ROM, Data RAM, and Data ROM
Interfacing to large external memory

Figure 14-18. 8051 Accessing 256Kx8 External NV-RAM
In some applications we need a large amount (256K. bytes, for example) of memory to store data. However, the 8051 can support only 64K bytes of external data memory since DPTR is 16-bit. To solve this problem, we connect AO – A15 of the 8051 directly to the external memory’s AO – A15 pins, and use some of the PI pins to access the 64K-byte blocks inside the single 256Kx8 memory chip. This is shown in Example 14-14, and illustrated in Figure 14-18.

Example 14-14
In a certain application, we need 256K bytes of NV-RAM to store data collected by an 8051 microcontroller, (a) Show the connection of an 8051 to a single 256Kx8 NV-RAM chip, (b) Show how various blocks of this single chip are accessed.
  1. The 256Kx8 NV-RAM has 18 address pins (AO – Al 7) and 8 data lines. As shown
    in Figure 14-18, AO – A15 go directly to the memory chip while A16 and A17 are
    controlled by Pl.O and Pl.l, respectively. Also notice that chip select of external
    RAM is connected to PI.2 of the 8051.
  2. The 256K bytes of memory are divided into four blocks, and each block is accessed
    as follows:

The DS89C4xO chip family has IK byte of SRAM, which is accessible by using the MOVX instruction. Next, we will show how to access this I K byte of SRAM in Assembly language. The C versions of these programs are given in the next section.
1K Byte of SRAM in DS89C4xO
The DS89C4xO family (DS89C420/30/40/50) comes with IK byte of SRAM embedded into the chip. This is in addition to the 256 bytes of RAM that comes with any 8052 chip such as the DS89C4xO. This IK byte (I KB) of SRAM can be very useful in many applications, especially for C compilers that need to store data variables. Another case in which this I K-byte RAM can be put to great

Figure 14-19. PMR Register Bits for IK-byte SRAM of DS89C4xO Chip
use is the tiny RTOS (real time operating systems) designed for the 8051 family. To access this IK byte of SRAM in the DS89C4xO chip, we must use the MOVX instruction. Notice that while accessing the 256 bytes of RAM in the 8052, we use either direct or register-indirect addressing modes, but to access the data stored in this 1KB of RAM, we must use the MOVX instruction. On power-on reset, the access to the 1KB SRAM is blocked. In order to access it, we must enable some bits in the SFR registers called PMR (power management register). The PMR is an SFR register and is located at address C4H. The SFR location C4H is one of the reserved byte spaces of the 8052 used by Dallas Semiconductor for PMR. The PMR bits related to the 1KB SRAM are shown in Figure 14-19. Examine the information in Figure 14-19 very carefully. The 1KB SRAM is not accessible upon reset. This is the default state that allows us to interface the DS89C4xO chip to external data memory, just like any member of the 8051/52 family. To access the 1KB SRAM, we must make PMR bits DEMO = 1 and DME1 = 0. In that case, any MOVX address of 0000 – 03FFH will go to the on-chip 1KB SRAM and all other addresses are directed to the external data memory. That means that if we want to add external data memory to the DS89C4xO chip we must designate it as 0400 – FFFFH since the first IK-byte space is already taken by the 1KB SRAM, assuming that the proper bits in the PMR are enabled. Again, it must be emphasized that upon reset, access to the 1 KB SRAM is blocked, and can be accessed only if we set the proper bits in the PMR register. This must be done every time we power up the DS89C4xO-based system. Study the next few examples to see how we access this 1KB SRAM.
Table 14-6: DS89C4xO Family from Maxim-Dallas Semiconductor

Example 14-15
Write a program (a) to enable access to the 1KB SRAM of the DS89C4xO, (b) put the ASCII numbers ’0′, ‘ 1′, and ’2′ in SRAM, and (c) read the same data from SRAM and send each one to ports PO, PI, and P2, respectively. Solution:

Example 14-16
Write a program (a) to enable access to the 1KB SRAM of the DS89C4xO, and (b) tran-
fer a block of data from RAM locations 40 – 44H into the IK SRAM.
Assume that we have the following data in the RAM location (256-byte space) starting
at 40H:

Example 14-17
Write a program in Assembly (a) to enable access to the 1KB SRAM of the DS89C4xO,
  1. move a block of data from code space of the DS89C4xO chip into 1KB SRAM, and
  2. then read the same data from RAM and send it to the serial port of the 8051 one byte
    at a time.

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