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Analog to Digital converter/conversion |
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ADCON0 |
A/D Control O; File08h (PIC16C71) |
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ADCON1 |
A/D Control 1; File 88h (PIC16C71) |
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ADCSn |
A/D Clock Select, bits 1:0 in the ADCON0 file register |
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ADIE |
A/D Interrupt Enable mask; INTCON[6] (PIC16C71X)/PIE1[6] |
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ADIF |
A/D Interrupt Flag; ADCON0[1] (PIC16C71X)/PIR1[6] |
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ADON |
A/D module ON; ADCON0[0] |
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ADRES |
A/D RESult; File09h/89h (PIC16C71X)/File 1Eh |
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ALU |
Arithmetic Logic Unit |
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ANn |
A/D input pinn |
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ANSII |
American National Standards Institution |
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ALU |
Arithmetic Logic Unit |
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ASCII |
American Standard Code for Information Interchange |
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BCD |
Binary Coded Decimal |
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BF |
Buffer Full; SSPSTAT[0] |
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C |
Carry flag in the Status register; STATUS[0] |
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CCP |
Capture/Compare PWM module |
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CCP1 |
CCP1 input/output pin (Common with RC2) |
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CCPR1H |
CCP Register 1 High byte; File 15h |
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CCPR1L |
CCP Register 1 Low byte; File 16h |
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CCP1CON |
CCP1 CONtrol register; File 1Dh |
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CCP1IE |
CCP1 Interrupt Enable mask; PIE1[2] |
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CCP1IF |
CCP1 Interrupt Flag; PIR1[2] |
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CCP2IE |
CCP2 Interrupt Enable mask; PIE2[0] |
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CCP2IF |
CCP2 Interrupt Flag; PIR2[0] |
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CCP1M |
CCP Mode control; CCP1CON[3:0] |
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CHSn |
A/D CHannel Select; ADCON[5:3] |
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CISC |
Complex Instruction Set Computer |
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CKP |
ClocK Polarity; SSPCON[4] |
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CMOS |
Complimentary Metal-Oxide Semiconductor |
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CREN |
Continuous Receive ENable; RCSTA[4] |
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CS |
Chip Select |
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CTS |
Clear To Send, RS-232 handshake signal |
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DAC (D/A) |
Digital to Analog converter/conversion |
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DC |
Digit Carry flag in the Status register; STATUS[1] |
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DC1B |
Duty Cycle 1 Bits; CCP1CON[5:4] |
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DCE |
Data Circuit terminating Equipment |
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DTE |
Data Terminal Equipment |
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ea |
Effective Address |
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EEADR |
EEPROM Address; File 09h or File 10Dh |
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EEADRH |
EEPROM Address High byte; File 10Fh |
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EECON1 |
EEPROM Control 1; File 88h or File 18Ch |
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EECON2 |
EEPROM Control 2; File 89h or File 18Dh |
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EEDATA |
EEPROM DATA; File 08h or File 10Ch |
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EEDATH |
EEPROM Data High byte; File 10Eh |
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EEIE |
EEPROM Interrupt Enable mask; INTCON[6] or PIE2[4] |
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EEIF |
EEPROM Interrupt Flag; EECON1[4] or PIR2[4] |
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EEPGD |
EEPROM Program/Data; EECON1[7]. |
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EEPROM |
Electrical Erasable PROM |
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EPROM |
Erasable PROM |
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FERR |
Framing Error; RCSTA[2] |
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FSR |
File Select Register; File 4 |
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GIE |
Global Interrupt Enable mask; INTCON[7] |
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GO/DONE |
ADC Start Convert (GO)/End Of Conversion (DONE); ADCON0[2] |
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GPR |
General-Purpose file Register |
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GPn |
General-purpose Register (I/O port) GPIO pinn |
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IC |
Integrated Circuit |
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I2C |
Inter-Integrated Circuit serial protocol |
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IDE |
Integrated Development Environment |
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IEC |
International Electro technical Commission |
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INDF |
Indirect File register; File 0 |
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INT |
External Interrupt input pin (Common with RB0) |
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INTCON |
Interrupt Control Register; File 0Bh |
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INTEDG |
External Interrupt Edge polarity selection; OPTION_REG[0] |
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INTE |
Interrupt Enable; INTCON[4] |
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INTF |
Interrupt Flag; INTCON[1] |
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I/O |
Input/Output |
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IRP |
Indirect addressing Register Page; STATUS[7] |
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ISR |
Interrupt Service Routine |
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LED |
Light-Emitting Diode |
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LSB |
Least Significant Bit or Byte |
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LSI |
Large Scale Integration |
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LSD |
Least Significant Digit |
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MCLR |
Master Clear reset pin |
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MCU |
Microcontroller Unit |
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MPU |
Microprocessor Unit |
|
ms |
Millisecond (10"3 s) |
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MSB |
Most Significant Bit or Byte |
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MSD |
Most Significant Digit |
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MSI |
Medium Scale Integration |
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ns |
Nanosecond (10"9 s) |
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OE |
Output Enable |
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OERR |
Overflow Error; RCSTA[1] |
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Operating System OS |
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OPTION_REG |
OPTION file Register; File 81 h |
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OTP |
One-Time Programmable (EPROM) |
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PC |
Program Counter |
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PC |
Personal Computer |
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PCFGn |
A/D Port Configuration; ADCON1[2:0] |
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PCL |
Program Counter Low byte; File 2 |
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PCLATH |
Program Counter Latch High byte; File 0Ah |
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PD |
Power Down sleep mode; STATUS[3] |
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PEIE |
Peripheral Interrupt Enable mask; INTCON[6] |
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PIC |
Peripheral Interface Controller |
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PIPO |
Parallel-In Parallel-Out register |
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PIE1 |
Peripheral Interrupt Enable register 1, File 8Ch |
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PIE2 |
Peripheral Interrupt Enable register 2, File 8Dh |
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PIR1 |
Peripheral Interrupt Register 1, File0Ch |
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PIR2 |
Peripheral Interrupt Register 2, File 0Dh |
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PISO |
Parallel-In Serial-Out shift register |
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PR2 |
Period Register for Timer 2; File 92h |
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PRNG |
Pseudo Random Number Generator |
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PROM |
Programmable ROM |
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PS |
Post/Prescale rate Select; OPTION_REG[2:0] |
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PSA |
Post/Prescale Scaler Assign; OPTION_REG[3] |
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PWM |
Pulse Width Modulation |
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RAn |
Register (port) A I/O pinn |
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RAM |
Random Access Memory |
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RBn |
Register (port)B I/O pinn |
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RBIE |
Register B Interrupt Enable; INTCON[3] |
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RBIF |
Register B Interrupt Flag; INTCON[0] |
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RBPU |
Register B Pull-UP; OPTION_REG[7] |
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RCIE |
ReCeive register Interrupt Enable mask; PIE1[5] |
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RCIF |
ReCeive register Interrupt Flag; PIR1[5] |
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RCREG |
ReCeive data REGister; File 1Ah |
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RCSTA |
ReCeive STAtus register; File 18h |
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RD |
ReaD; EECON1[0] file register |
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REn |
Register (port)E I/O pinn |
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RISC |
Reduced Instruction Set Computer (see CISC) |
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ROM |
Read-Only Memory |
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RPn |
Register Page bits; STATUS[6:5] |
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rtl |
Register Transfer Language |
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RTS |
Ready To Send, RS-232 handshake signal |
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RX |
ReCeive pin for USART (common with RC7) |
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RX9 |
ReCeive 9-bit data control; RCSTA[6] |
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RTCC |
Real Time Counter/Clock (see Timer 0) |
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SAR |
Successive Approximation Register |
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SCK |
Serial Clock in SPI protocol |
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SDI |
Serial Data Input in SPI protocol |
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SDO |
Serial Data Output in SPI protocol |
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SIPO |
Serial-In Parallel-Out shift register |
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SISO |
Serial-In Serial-Out shift register |
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SP |
Stack Pointer |
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SPBRG |
Serial Port Baud-Rate Generator; File 99h |
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SPEN |
Serial Port Enable; RCSTA[7] |
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SPI |
Serial Peripheral Interface protocol |
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SPR |
Special-Purpose file Register |
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SSP |
Synchronous Serial Port |
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SSPBUF |
SSP Buffer register; File 13h (PIC16C7X) |
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SSPCON |
SSP Control file Register, File 14h |
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SSPEN |
SSP Enable; SSPCON[5] |
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SSPIE |
SSP Interrupt Enable mask; PIE1[3] |
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SSPIF |
SSP Interrupt Flag; PIR1[3] |
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SSPM |
SSP Mode control; SSPCON[3:0] |
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SSPSR |
SSP Shift Register (PIC16C7X) |
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STATUS |
Status Register; File3 |
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SYNC |
Synchronous mode in the USART; TXSTA[4] |
|
To |
Watchdog Time Out; STATUS[4] |
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T0CKI |
Timer 0 ClocK Input pin (Common with RA4) |
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T0CS |
Timer 0 Clock Select; OPTION_REG[5] |
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T0IE |
Timer 0 Interrupt Enable mask; INTCON[5] |
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T0IF |
Timer 0 Interrupt Flag; INTCON[2] |
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T1CKI |
Timer 1 Clock Input pin (Common with RC0) |
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T1CON |
Timer 1 Control register; File 10h |
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T2CON |
Timer 2 Control register; File 12h |
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T1OSCEN |
Timer 1 Oscillator Enable; T1CON[3] |
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T1SYNC |
Timer 1 Synchronize; T1CON[2] |
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TMR0 |
TiMeR0 file register; File 1 |
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TMR1CS |
Timer 1 Clock Select; T1CON[1] |
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TMR1H |
Timer 1 High byte file register; File 0Fh |
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TMR1IE |
Timer 1 Interrupt Enable mask; PIE1[0] |
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TMR2IE |
Timer 2 Interrupt Enable mask; PIE1[1] |
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TMR1IF |
Timer 1 Interrupt Flag; PIR1[0] |
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TMR2IF |
Timer 2 Interrupt Flag; PIR1[1] |
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TMR1L |
Timer 1 Low byte file register; File 0Eh |
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TMR1ON |
Timer 1 ON; T1C0N[0] |
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TOUTPS |
Timer 2 Output Post Scalar; T2C0N[3:0] |
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TRISA |
TRI State A (Data Direction register A) File register, File 85h |
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TRISB |
TRI State B (Data Direction register B) File register, File 86h |
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TRISC |
TRI State C (Data Direction register C) File register, File 87h |
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TRISD |
TRI State D (Data Direction register D) File register, File 87h |
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T0SE |
Timer 0 Set Edge; OPTION_REG[4] |
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TTL |
Transistor Transistor Logic family |
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TTY |
Tele Typewriter |
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TX |
Transmit pin for USART (Common with RC6) |
|
TXEN |
Transmit register Enable; TXSTA[5] |
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TXIE |
Transmit register Interrupt Enable mask; PIE1[4] |
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TXIF |
Transmit register Interrupt Flag; PIR1[4] |
|
TXREG |
Transmit data Register; File 19h |
|
TXSTA |
Transmit Status register; File 98h |
|
|s |
Microsecond (10"6 s) |
|
UART |
Universal Asynchronous Receiver Transmitter |
|
USART |
Universal Synchronous-Asynchronous Receiver Transmitter |
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Vdd |
Positive (Drain) supply voltage |
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Vee |
Earth (0 V) supply voltage |
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Vpp |
Positive Programming voltage |
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VLSI |
Very Large-Scale Integration |
|
W |
Working register |
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WCOL |
Write Collision; SSPCON[7] |
|
WR |
Write; EECON1[1] |
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WREN |
Write Enable; EECON1[2] |
|
WRERR |
Write Error; EECON1[3] |
|
Z |
Zero flag in the Status register; STATUS[2] |
