The Real World Part 1 (PIC Microcontroller)

Up to this point we have mainly concentrated on how the software has interacted with the processor’s internal registers and Data memory. Now, as a prelude to how the MCU relates to its internal peripheral devices and hence monitors and controls its external environment, i.e. the real world outside its pins, we need to look at external support issues, such as power supply requirements, clocking and resetting. After reading this topic you will:

• Be familiar with the permitted range of power supply and input/output voltages.

• Distinguish between quiescent and dynamic power dissipation and recognize that the latter is directly proportional to both frequency and to the square of the supply voltage.

• Be aware of how the sleep mode is invoked and exited, and its effect on the processor.

• Understand the basics of the integral clock oscillator.

• Know how the PIC’s configuration can be set up during programming.

• Understand the various nuances of the Reset process.

Figure 10.1 gives the external view of some typical PIC family members, ranging from the minuscule 8-pin 12-bit PIC12C508/9, which features one 5-bit general-purpose parallel I/O port, a Timer and | Kbyte Program store and 25/41 file registers through to the jumbo 40-pin 14bit PIC16F877 which has a 8 Kbyte flash memory Program store, 368 file registers, 33 bits of parallel I/O, three Timers, a 10-bit A/D converter, several serial port formats and a 256-byte EEPROM Data module. We are going to mainly concentrate on the 18-pin PIC16F83/41 and the 40-pin PIC16C74, but most of the characteristics are similar across all PIC families. Where relevant, other family members will be used as the exemplar; particularly the PIC16C7X and PIC16F87X devices.


All members of the PIC family will operate typically with a supply voltage VDD of nominally 5 V. The standard PIC16F84 can operate over the range 5 ± 1V in all but the high-speed crystal clock mode (4-10 MHz) where the range is restricted to 5 ± 0.5 V. The PIC16LF83/4 low-power variant, which is restricted to 2 MHz, can operate over the range 2-6 V. The PIC 12C5XX family has an allowable range of 2.5-5.5 V for up to 4 MHz.

Pinout for a variety of PIC family members.

Fig. 10.1 Pinout for a variety of PIC family members.

The logic 0 output voltage VOL is 0.6 V maximum for low and a minimum output high voltage VOH of VDD – 0.7 V. Input voltages generally are accepted as low VIL if below 0.16VDD. A high input VIH is usually accepted as logic 1 if above 0.5VDD.2

All the devices shown in Fig. 10.1 have a quoted typical current consumption of:

• < 2 mA at VDD = 5 V clocked at 4 MHz;

• 15 ^A at 3 V and 32 kHz;

• < 1 nA on standby in the Sleep state.

Many microcontroller applications are battery powered and in such situations power consumption is critical. These bare figures from the data sheets show a variation of 1:2,000,000 so it is important that the factors influencing current be understood.

The relationship between the PIC’s clocking frequency and current is graphed in Fig. 10.2. Clearly power dissipation VDD x IDD is directly proportional to operating frequency. For instance, one hundred times more current is required at 10 MHz as compared to 100 kHz.

To see why this is so, consider a switch charging and discharging a ca-pacitive load C, as in Fig. 10.3. The switch is implemented by a transistor and the load is due to the stray capacitance of the connection to the next field-effect transistor and its input gate. RS represents the resistance of the switching transistor.

When this capacitance is charged up to V volts (switch opens), ^CV2 Joules of energy is stored. Energy is dissipated in the load by this charging current as follows:

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Thus in going high, | CV2 Joules are dissipated in the load resistance (irrespective of its value Rl!) and ^CV2 Joules are stored in the capacitor’s electric field. On discharge, this stored energy is dissipated in Rs// Rl (once again irrespective of value). The energy dissipated in one switching cycle is then CV2 Joules. The total power is this figure multiplied by the number of cycles per second (CV2 f), plus any quiescent dissipation.

The preceding relationship CV2f shows that dissipated power is proportional to frequency for any given supply voltage. Furthermore, it is proportional to the square of the supply voltage, so halving VDD from 5 V to 2.5 V should quarter the power dissipation VDD x IDD.3

Typical supply current versus clocking frequency.

Fig. 10.2 Typical supply current versus clocking frequency.

The dynamic power dissipation derived above should be added to that due to the quiescent current that the device consumes when the clocking rate is dropped to zero. In the case of the PIC16F84 this power-down current IPD is quoted in the data sheet as typically 1 nA with a VDD of 4 V and 16nA worst case. The PIC12C5XX has equivalent values quoted at VDD of 3 V of 0.3 nA and 5 nA respectively.

Of course not clocking a digital circuit is rather unproductive. All PIC families feature a Sleep mode which effectively turns off the internal clock oscillator. This switch is actioned in software using the sleep instruction. Once asleep the contents of the Data store are retained pro-vided that the supply voltage remains above 1.5 V. The PIC can be awakened either by Resetting the device, by an enabled interrupt from outside or if the enabled Watchdog timer overflows. If the Global Interrupt Enable mask (GIE) is clear then the processor will simply execute the instruction after sleep and continue on as normal. If GIE is set then after the instruction following sleep is executed, the processor will go to the Interrupt Service Routine as a normal interrupt response.

Equivalent output circuit, where C represents both intrinsic and external load capacitance.

Fig. 10.3 Equivalent output circuit, where C represents both intrinsic and external load capacitance.

To ready the processor to be awakened by any specific external interrupt source; for example by a request on the RB0/INT pin, the appropriate local flag bit (INTF in this instance) must be cleared and the corresponding mask bit (INTE in this instance) must be set. Following the sleep instruction, the programmer must reset the interrupt flag.

When the processor executes a sleep instruction it will clear the PD (Power Down) bit in the Status register and the internal clock oscillator is turned off. If the Watchdog timer is enabled at that time then it will be cleared, including its prescaler, but will continue to run as it has its own private internal oscillator. At this time the TO (Time Out) flag will be set (i.e. no Time Out). All file register contents, including the various port settings, remain unchanged.

If an enabled interrupt occurs before the sleep instruction is executed; that is the interrupt flag is set on entry, then sleep is executed as a nop (No Operation). In this situation the PD bit will not be cleared, so the programmer can determine, if necessary, after a sleep instruction if the PIC really did go through an dormant period. The software can also determine if the processor was awakened by the Watchdog timing out, by checking to see if the TO bit in the Status register has been cleared. Normally in Watchdog-enabled applications, the sleep instruction is followed by a clrwdt (CLeaR WatchDog Timer) instruction. Checking the appropriate Interrupt flag in the INTCON register will determine if the source of the awakening was an interrupt.

Whatever the source of the awakening there will be a delay of 1024 clock cycles fOSC before processing of the instruction following the sleep breakpoint. This is to ensure that the crystal clock oscillator has started up and stabilized. This oscillator startup delay, illustrated in Fig. 10.7, is not implemented if the PIC is using a resistor-capacitor clock mode of Fig. 10.4(b) and itemized in Table 10.2.

The power down current IPD is lower when the Watchdog timer is not enabled; for example; for the PIC16F84 IPD is quoted as typically 1.0 nA (16 nA maximum) and 7 nA (28 nA maximum) with the Watchdog timer disabled/enabled respectively. Figures are given for a VDD of 4 V I/O ports set to input and pins tied to either VDD or VSS (usually ground).

All members of the PIC family have an integral oscillator circuit which when completed with timing elements provide the internal clocking waveforms shown in Fig. 4.4.The PIC12C5XX family have an optional internal RC timing elements giving a nominal 4 MHz clocking rate and allow the oscillator pins OSC1 and OSC2 to used as general-purpose parallel input/output lines – GP4 and GP5 in Fig. 10.1(a).

Typical oscillator configurations.

Fig. 10.4 Typical oscillator configurations.

The PIC16CXXX family can be operated in one of four different oscillator modes. These are:

• LP (Low Power) for crystal timing elements below around 200 kHz, eg. a 32.768 kHz watch crystal.

• XT for both crystals and ceramic resonators up to 4 MHz.

• HS for high speed crystals and ceramic resonators above 4 MHz.

• RC for low cost external resistor/capacitor timing elements.

The 12C5XX family members call the RC mode EXTRC (External RC) to distinguish this from the INTRC (Internal RC) mode.

We see from Fig. 10.4(a) that the three crystal-mode oscillator configurations comprise an inverting amplifier, which is disabled by the sleep instruction, together with the user-supplied timing elements. The only difference between modes is the value of the inverting amplifier’s gain. In the LP mode the gain is lowest and power consumption is minimised. The HS mode is used for high frequencies and has the largest current requirement. In general the oscillator option with the lowest possible gain should be used. The target device’s data sheet will give details of range and component values.

The PIC16F84A can be clocked up to 20 MHz.4. Most other mid-range PIC devices come in similar clocking ratings. The PIC12C5XX family is limited to 4 MHz and does not have a HS mode.

A typical 10 MHz system uses a 10 MHz AT-cut crystal with a C1 of 22 pF and a C2 of 33 pF in the HS mode. A 32 kHz crystal needs a C1 of 68 pF and a C2 of 100 pF in the LP mode. Although both capacitors may have the same value, making C2 larger improves the oscillator start-up characteristics after reset and awakening from the Sleep state. Some crystals in the HS mode may require a series resistor at the OSC2 pin. Details are given in Microchip’s application note PIC16/17 Oscillator Design. Ceramic resonators are less expensive than crystals but have an inferior frequency accuracy of the order of 0.5% and temperature stability is poorer. Ceramic resonators may come with integral capacitors to reduce the part count. Microchip’s application note AN588 gives a comparison between ceramic resonators and crystals used in this application.

As an alternative the PIC may be driven from an external oscillator. This can be useful if several devices are to be synchronised to the one clock. In such cases, the external oscillator should drive the OCS1 pin and OSC2 either left open or grounded via a resistor to reduce noise. The oscillator should have a low level V|L below 0.3VDD and a high level above 0.7VDD.5 The PIC should be set to the crystal mode (as opposed to RC) appropriate to the frequency.

The RC mode is useful for low-cost applications where the actual clocking rate and stability is not of importance. The rate is dependent on the external resistor R1 and C1 and supply voltage VDD in a complex manner. Generally, the chosen device’s data sheet will give tables and graphs showing typical frequencies against these variables. For example, the PIC16C7X devices will have an average clocking rate of 1.92 MHz ± 9.5% for a VDD of 5 V, R1 of 3.3kQ, C1 of 100pF at 25°C. Of course the tolerance and temperature variation of the timing components and VDD must be considered.

The PIC125XX family have integral RC components which give a nominal 4 MHz clock rate. This releases the OSC1 pin for use as a general-purpose port input/output pin GP5. The actual clocking rate can be varied slightly by software by means of a calibration SPR file register.

PICs in the RC/EXTRC mode have the system clock (FOSC/4) available at OSC2 which can be buffered and used as a system clock to synchronize other components or PICs. In the PIC125XX family this facility may be disabled and the OSC2 pin used as a general-purpose port I/O pin GP4.

Our discussion on the configuration of the on-board oscillator covered four modes. Besides the oscillator modes, the Watchdog timer may be enabled or disabled and various other options chosen depending on the family device. For the particular case of the PIC16F83/4 there are four main modes, the oscillator having four submodes.

• Four oscillator submodes.

• Watchdog timer enable/disable.

• Power-up timer enable/disable.

• Code protection enable/disable.

These modes can be configured by raising the MCLR pin to 13 V which places the PIC device into its Program/Verify mode; see Fig. 10.5(a). In this state, outside circuitry, usually the device programmer, has access to the Program store and can burn in the application code. The Device programmer also has access to certain private Program store locations which are not visible when the PIC is running normally. Specifically, the mid-range PIC family reserve ‘secret’ location 2007h as their configuration word.6

Setting each bit, sometimes known as a fuse, in the configuration word to the appropriate value ensures that when the MCU is in its normal running mode the clock oscillator and other facilities will be configured appropriately. All PICs have the fuses shown in Fig. 10.5(b) but they may be disposed differently and additional configuration options may be supported depending on the family member’s architecture.

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