Stored Program Processing Part 2 (PIC Microcontroller)

Although our program doesn’t do very much, it only takes around 1 ^s to implement each instruction. A million unimpressive operations each second can amount to a great deal! Nevertheless, it hardly rates highly in the annals of software, so we will wrap up our introduction to computing by looking at some slightly more sophisticated examples.

Writing a program is somewhat akin to building a house. Given a known range of building materials, the builder simply puts these together in the right order. Of course there are tremendous skills in all this; poor building techniques lead to houses that leak, are drafty and eventually may fall down!

It is possible to design a house at the same time as it is being built. Whilst this may be quite feasible for a log cabin, it is likely that the final result will not remain rain proof very long, nor will it be economical, maintainable, ergonomic or very pretty. It is rather better to employ an architect to design the edifice before building commences. Such a design is at an abstract level, although it is better if the designer is aware of the technical and economic properties of the available building materials.

Unfortunately much programming is of the ‘on the hoof’ variety, with little thought of any higher-level design. In the software arena this means devising strategies and designing data structures in memory. Again, it is better if the design algorithms keep in mind the materials of which the program will be built; in our case the machine instructions.

At the level of our examples in this topic, it will be this coding (building) task we will be mostly concerned with. Later topics will cover more advanced structures which will help this process, and we will get more practice at devising strategies and data structures.

In order to code software we must have a knowledge of the register architecture of the computer/microcontroller and of the individual instructions. Figure 3.5 shows the programming model we will use for our exercises. This shows all registers that can be ‘got at’ by the programmer.

I have added three registers to the previous complement that actually are part of the Data store rather than the CPU but have a special significance for the programmer. File 0 and File 4 are a pair of Address registers working in tandem to point to an object in memory, as described further on in Fig. 3.6. The Status Register6 STATUS comprises two bits in File 3 that are used to tell the software something about the outcome from an instruction. Thus the C flag (bit0 in File 3) primarily holds the Carry out from the last Addition operation. For instance (in decimal) 5 + 2 = 7C0; 5 + 9 = 4C1. It also functions as the complement of the Borrow out from a Subtraction operation. For example 5 – 2 = 3B1; 5 – 9 = 6B0. The Z flag (bit 2 in File 3) is set if the result of the last operation is zero.

Table 3.1 shows all the instructions supported by the BASIC computer. Before looking at these, let us discuss the concept of the address mode. Most instructions act on data, which may be in internal CPU registers or out in the Data store. Thus the location of such operands must be part of the instruction. It isn’t sufficient to simply state clr – Clear what? There are different ways of specifying the operand location. These are known as address modes.

Table 3.1: Our BASIC computer’s instruction set.








Add W and F

tmp18-99 tmp18-100 tmp18-101 tmp18-102 tmp18-103

Add Literal and W

tmp18-104 tmp18-105 tmp18-106 tmp18-107 tmp18-108

Clear F

tmp18-109 tmp18-110 tmp18-111 tmp18-112 tmp18-113

Clear W

tmp18-114 tmp18-115 tmp18-116 tmp18-117 tmp18-118

Increment F

tmp18-119 tmp18-120 tmp18-121 tmp18-122 tmp18-123

Decrement F

tmp18-124 tmp18-125 tmp18-126 tmp18-127 tmp18-128

Subtract W from F

tmp18-129 tmp18-130 tmp18-131 tmp18-132 tmp18-133

Subtract W from L

tmp18-134 tmp18-135 tmp18-136 tmp18-137 tmp18-138


Move F

tmp18-139 tmp18-140 tmp18-141 tmp18-142 tmp18-143

Move W to F

tmp18-144 tmp18-145 tmp18-146 tmp18-147 tmp18-148

Move Literal to W

tmp18-149 tmp18-150 tmp18-151 tmp18-152 tmp18-153


AND W and F

tmp18-154 tmp18-155 tmp18-156 tmp18-157 tmp18-158

AND Literal and W

tmp18-159 tmp18-160 tmp18-161 tmp18-162 tmp18-163

Complement F

tmp18-164 tmp18-165 tmp18-166 tmp18-167 tmp18-168

Inclusive OR W and F

tmp18-169 tmp18-170 tmp18-171 tmp18-172 tmp18-173

Inclusive OR Literal and W

tmp18-174 tmp18-175 tmp18-176 tmp18-177 tmp18-178

Rotate left F

tmp18-179 tmp18-180 tmp18-181 tmp18-182 tmp18-183

Rotate right F

tmp18-184 tmp18-185 tmp18-186 tmp18-187 tmp18-188

exclusive OR W and F

tmp18-189 tmp18-190 tmp18-191 tmp18-192 tmp18-193

exclusive OR Literal and W

tmp18-194 tmp18-195 tmp18-196 tmp18-197 tmp18-198

Skip and Jump

Bit Test F, Skip if Clear

tmp18-199 tmp18-200 tmp18-201 tmp18-202 tmp18-203

Bit Test F, Skip if Set

tmp18-204 tmp18-205 tmp18-206 tmp18-207 tmp18-208

Decrement F, Skip if Zero

tmp18-209 tmp18-210 tmp18-211 tmp18-212 tmp18-213

Go to address

tmp18-214 tmp18-215 tmp18-216 tmp18-217 tmp18-218

Increment F, Skip if Zero

tmp18-219 tmp18-220 tmp18-221 tmp18-222 tmp18-223

: Flag operates normally

: Flag not affected


: Effective address


: Bitb (0-7) in file


: Carry or Borrow, bit0 in F3


: Zero, bit 2 in F3


: Destination; 0 = W, 1 = file


: Working register


: 8-bit Literal


: Equivalent to


: Increment

: Decrement


: IF A is True THEN DO S1 ELSE DO S2




A few instructions, not shown in Table 3.1, do not explicitly refer to any location. For example return for RETURN from subroutine..

Register Direct

Here the operand is specified to be in the Working register. For example:


Most instructions specify at least one operand should be in W. In many cases W can be both a source and the destination operand. For instance:


where W initially holds one of the two source datum bytes, and ends up holding the outcome datum.


This address mode is used to specify an operand which is constant data rather than a location. For example:


Only special literal instructions are used with this type of data, such as movlw and sublw. The destination of this type of instruction is always W. The sublw instruction sometimes causes confusion as it actually takes away the contents of W from the literal byte and not vice versa. Thus sublw 1 does not subtract one from the contents of W (i.e. decrement W) but 1 – W. To decrement the contents of W use addlw -1 (i.e. addlw 0FFh). Note the use of the # symbol in the rtl description to denote that the following number is constant data.

A few instructions can test or modify a single bit in a File. For instance:


in which Operand B is the fixed literal 6, specifying the bit position in Operand A’s specified File.

In both kinds of literal instruction the constant is encoded as part of the instruction word. In the former, eight bits of the 14-bit word is used, and in the latter three bits.

File Direct

Here the totally fixed file address of the operand, either source or/and destination is directly specified. For example:


clears the byte out at File 20h.

In many cases the same file can be both source and destination. Thus:


as opposed to the Working register:


which uses File Direct addressing for Operand A and Register Direct for Operand B.

The main characteristic of this address mode is that the location of the operand is fixed as an integral part of the program, and thus cannot be changed as execution progresses. Although directly specifying its address may seem to be the obvious way to locate an object in the Data store, in some situations this technique is rather inflexible.

Suppose we wished to clear all file registers from 0Ch through to 3Fh in the File store, say to hold an array of 52 byte elements. The obvious way to do this is shown in Program 3.1, which uses a clrf instruction for each byte. Although it works, it is rather inefficient, and the mind boggles if you wanted to clear, say, a 1 Kbyte File store. There has got to be a better way!

Program 3.1 Clearing a block of files the linear way.

tmp18-234 tmp18-235
tmp18-236 tmp18-237
tmp18-238 tmp18-239
tmp18-240 tmp18-241
tmp18-242 tmp18-243
tmp18-244 tmp18-245
tmp18-246 tmp18-247
tmp18-248 tmp18-249
tmp18-250 tmp18-251


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