Semiconductor Nanowires: Nanoscale Electronics and Optoelectronics Part 3 (Nanotechnology)

Photodetectors

In addition to generating photons via carrier recombination in nanoscale NW devices, absorbed photons can produce electrical carriers, which when measured, serve as the basis for Lilliputian photodetectors.[49]

The striking PL polarization anisotropy makes these NWs ideally suited for polarization sensitive photonic devices such photodetectors and optically gated switches. For example, a polarization sensitive photodetector can be easily fabricated by making metallic contacts to both ends of individual NWs (Fig. 21A). The conductance (G) of individual NWs was found to increase by 2-3 orders of magnitude with increasing laser intensity (Fig. 21B), and these changes were reproducible and reversible, which indicate that the increases in G are due to direct carrier collection at the NW-metal contacts.

Polarized photodetection using individual InP NWs. (A) Schematic depicting the use of a NW as a photodetector. Inset: SEM image of a 20 nm diameter NW and contact electrodes for photoconductivity (PC) measurements. (B) Conductance, G, vs. excitation power density for excitation light polarized parallel and perpendicular to the NW axis. Inset: PC anisotropy vs. excitation power. (C) Conductance vs. polarization angle as the polarization was manually rotated while measuring the PC.


Fig. 21 Polarized photodetection using individual InP NWs. (A) Schematic depicting the use of a NW as a photodetector. Inset: SEM image of a 20 nm diameter NW and contact electrodes for photoconductivity (PC) measurements. (B) Conductance, G, vs. excitation power density for excitation light polarized parallel and perpendicular to the NW axis. Inset: PC anisotropy vs. excitation power. (C) Conductance vs. polarization angle as the polarization was manually rotated while measuring the PC.

In addition, a large polarization anisotropy was also observed in the photoconductivity (Fig. 21C). The photoconductivity anisotropy, a = (G\\ — G?)/ (G\\ + G?), values were similar to the PL anisotropy and the theoretical predictions described above. The large anisotropy shows that the conductance of devices is essentially switched on and off while the polarization of the incident light is changed. The overall sensitivity of the photodetector can be gauged by the responsivity, which is the ratio of photocurrent vs. absorbed optical power. For the device shown in Fig. 34, the responsivity is about 3000 A/W, which is an impressive number, considering that this device was not optimized.[62]

There are several unique features of these NW-based photodetectors that could enable applications. First, the sensitivity and polarization anisotropy is nearly independent of excitation wavelength for energies larger than band gap. In addition, it is easily possible to make a device that simultaneously measures intensity and polarization by using two crossed NWs and measuring their photoconductivity independently. Second, the active device element in the NW-based photodetector is substantially smaller than other polarization sensitive quantum-well based detec-tors,[63,64] which are not smaller than 50 x 50 mm and usually only sensitive to a very specific wavelength. Lastly, the extremely small size of these devices may open the possibility of creating ultra high-speed detectors.

Summary

Overall, we have shown that semiconductor NWs can be used to assemble a wide range of photonic and optoelectronic devices, including LEDs, lasers, and photodetectors. The availability of such nanoscale optoelectronic devices can open many exciting opportunities in nanoscale science and technology. Nanoscale light source and detectors may lead to exciting opportunities in photonics. The nanoscale light sources can be used for ultrahigh resolution imaging, sensing, and analysis in lab-on-a-chip systems as well in telecommunications and information storage. For example, nanoscale emitters can be readily used as the excitation source for a variety of materials. Nanowire photodetectors can be exploited as optically gated switches. When nanoscale light sources and photo-detectors are combined together, it is possible to create high-density, high-speed interconnects for electronic and/or photonic circuits, where polarization sensitivity can vastly increase the information bandwidth.

Considering the wide range of group IV, III-V, and II-VI semiconductor NW materials available, it should be possible to assemble in the future a variety of NW-based light sources and detector arrays for further into infrared spectral regimes, including the 1.5 mm regime that is critical to current optical communications. In addition, the extremely small size of these structures could also lead to fundamentally new types of device such as single photon sources,[65,66] which could enable quantum information encryption and possibly optical schemes for quantum computation.

HIERARCHICAL ASSEMBLY NANOWIRES

A key motivation underlying research on nanoscale devices is the potential to achieve integration at a level not possible in conventional microelectronics. To achieve this goal in future nanosystems will require the development and implementation of efficient and scalable strategies for assembly of nanoscale building blocks into increasingly complex architectures. First, methods are needed to assemble NWs into highly integrated arrays with controlled orientation and spatial position. Second, approaches must be devised to assemble NWs on multiple length scales and to make interconnects between nano-, micro-, and macroscopic worlds. To address these critical next levels of organization, we have focused significant effort on developing complementary strategies for hierarchical assembly of NWs on surfaces, and describe two promising approaches below.

Electrical Field Directed Assembly

Applied electric fields (E-fields) can be used effectively to attract and align NWs due to their highly anisotro-pic structures and large polarizabilities (Fig. 22).[33] This underlying idea of E-field directed assembly can be readily seen in images of NW solutions aligned between parallel electrodes (Fig. 22B), which demonstrate that virtually all of the NWs aligned in parallel along the E-field direction. Electric field directed assembly can also be used to position individual NWs at specific positions with controlled directionality. For example, E-field assembly of NWs between an array of electrodes (Fig. 22C) clearly shows that individual NWs can be positioned to bridge pairs of diametrically opposed electrodes and form a parallel array. In addition, by changing the E-field direction with sequential NW solutions, the alignment can be carried out in a layer-by-layer fashion to produce crossed NW junctions (Fig. 22D). These results demonstrate clearly that E-field directed assembly can be used to align and position individual NWs into parallel and crossed arrays, which correspond to two basic geometries for integration, and thus provide one robust approach for rational and parallel assembly of nanoscale device arrays.

E-field directed assembly of NWs. (A) Schematic view of E-field alignment. (B) Parallel array of NWs aligned between two parallel electrodes. (C) Spatially positioned parallel array of NWs obtained following E-field assembly. The top inset shows 15 pairs of parallel electrodes with individual NWs bridging each diametrically opposed electrode pair. (D) Crossed NW junction obtained using layer-by-layer alignment with the E-field applied in orthogonal directions in the two assembly steps.

Fig. 22 E-field directed assembly of NWs. (A) Schematic view of E-field alignment. (B) Parallel array of NWs aligned between two parallel electrodes. (C) Spatially positioned parallel array of NWs obtained following E-field assembly. The top inset shows 15 pairs of parallel electrodes with individual NWs bridging each diametrically opposed electrode pair. (D) Crossed NW junction obtained using layer-by-layer alignment with the E-field applied in orthogonal directions in the two assembly steps.

Fluid Flow Directed Assembly

MicroChannel fluidic device

Electric field directed assembly, which represents the first approach described for assembly of 1D nanostruc-tures, also has limitations, including 1) the need for substantial conventional lithography to pattern micro-electrode arrays used to produce aligning fields, and 2) the deleterious effect of fringing electric fields at the submicron length scales. To achieve a greater flexibility in rational, parallel assembly of 1D nano-structures into nanosystems, we have developed a powerful new approach called fluidic flow directed assembly.[36] In this method, NWs (or NTs) can be easily aligned by passing a suspension of NWs through microfluidic channel structures, for example, formed between a poly(dimethylsiloxane) (PDMS) mold[67] and a flat substrate (Fig. 23). Parallel and crossed NW arrays can be readily created using single (Fig. 23A) and sequential crossed (Fig. 23B) flows, respectively, for the assembly process.

Fluid flow directed assembly NWs. (A) A channel is formed when a trench structure is brought in contact with a flat substrate. Nanowire assembly is carried out by flowing a NW suspension through the channel at a controlled rate and for a set duration. Parallel arrays of NWs are observed in the flow direction on the substrate when the trench structure is removed. (B) Crossed NW arrays can be obtained by changing the flow direction sequentially in a layer-by-layer assembly process.

Fig. 23 Fluid flow directed assembly NWs. (A) A channel is formed when a trench structure is brought in contact with a flat substrate. Nanowire assembly is carried out by flowing a NW suspension through the channel at a controlled rate and for a set duration. Parallel arrays of NWs are observed in the flow direction on the substrate when the trench structure is removed. (B) Crossed NW arrays can be obtained by changing the flow direction sequentially in a layer-by-layer assembly process.

Parallel assembly of nanowire

Images of NWs assembled on substrate surfaces (Fig. 24A) within microfluidic flows demonstrate that virtually all of the NWs are aligned along the flow direction. This alignment readily extends over hundreds of micrometers (Fig. 24B). Indeed, alignment of the NWs has been found to extend up to millimeter length scales, and is limited only by the size of the fluidic channels used. The alignment of NWs within the channel flow has been explained within the framework of shear flow.[68,69] Specifically, the channel flow near the substrate surface resembles a shear flow and aligns the NWs in the flow direction before they are immobilized on the substrate. This idea readily provides the intellectual underpinning needed for controlling the degree of alignment and average separation of the NWs. First, higher flow rates produce larger shear forces and will lead to better alignment, and thus the flow rate can be used to control the degree of alignment. Indeed, the width of the NW angular distribution with respect to the flow direction significantly narrows with increasing flow rate (Fig. 24C). Studies of the distribution widths measured over a range of flow conditions showed that the width decreased quickly as flow increased to a nearly constant value at —10 mm/sec (where more than 80% of the NWs are aligned within ±5° of the flow direction (Fig. 24C, inset).

 Parallel assembly of NW arrays. (A) SEM image of a parallel array of InP NWs aligned by flow. (B) Optical microscope image of a parallel array of InP NWs aligned over very large area. (C) NW angular spread with respect to the flow direction vs. flow rate. The inset shows histogram of NW angular distribution at a flow rate of 9.40 mm/sec. (D) Average density of NWs vs. flow time.

Fig. 24 Parallel assembly of NW arrays. (A) SEM image of a parallel array of InP NWs aligned by flow. (B) Optical microscope image of a parallel array of InP NWs aligned over very large area. (C) NW angular spread with respect to the flow direction vs. flow rate. The inset shows histogram of NW angular distribution at a flow rate of 9.40 mm/sec. (D) Average density of NWs vs. flow time.

Second, these studies[36] demonstrated that the average NW density could be controlled by the flow duration (Fig. 24D). Experiments carried out at constant flow rate show that the NW density increases systematically with flow duration, and can, upon extended deposition time, produce NW arrays with spacings of the order of 100 nm or less. The relationship between average separation and flow duration also depends on and can be further controlled by the chemical functionality on the NW and substrate surfaces; that is, strong complementary interactions will facilitate deposition from the flow.

Crossed nanowire arrays

The fluidic flow assembly approach can be used to organize NWs into more complex crossed structures, which are critical for building dense nanodevice arrays, using a layer-by-layer deposition process (Fig. 23B). The formation of crossed and more complex structures requires that the nanostructure-substrate interaction is sufficiently strong that sequential flow steps do not affect preceding ones: We find that this condition is readily achieved. For example, alternating the flow in orthogonal directions in a two-step assembly process yields crossbar structures in high yield (Figs. 25A,B). These data demonstrate that crossbars extending over 100s of microns on a substrate with only 100s of nanometers separation between individual cross points are obtained through a very straightforward, parallel low cost, and fast process.

Layer-by-layer assembly of crossed NW arrays. (A, B) Typical optical microscope and SEM images of crossed arrays of InP NWs obtained in a two-step assembly process with orthogonal flow directions for the sequential steps. Arrows indicate the two flow directions. (C) An equilateral triangle of GaP NWs obtained in three-step assembly process, with flow directions highlighted by arrows.

Fig. 25 Layer-by-layer assembly of crossed NW arrays. (A, B) Typical optical microscope and SEM images of crossed arrays of InP NWs obtained in a two-step assembly process with orthogonal flow directions for the sequential steps. Arrows indicate the two flow directions. (C) An equilateral triangle of GaP NWs obtained in three-step assembly process, with flow directions highlighted by arrows.

Fluidic flow directed assembly of multiple crossed NW arrays offers significant advantages over previous efforts. First, it is intrinsically very parallel and scalable with the alignment readily extending over very large length scales. Second, this approach is general for virtually any elongated nanostructure including carbon NTs and DNA molecules. Third, it allows for the directed assembly of geometrically complex structures by simply controlling the angles between flow directions in sequential assembly steps. For example, equilateral triangles (Fig. 25C) were easily assembled in a three-layer deposition sequence using 60° angles between the three flow directions. The method of flow alignment thus provides a flexible way to meet the requirements of many device configurations in the future. An important feature of this layer-by-layer assembly scheme is that each NW layer can be independent of the preceding one(s), and thus a variety of homo- and hetero-junction configurations can be obtained at each crossed point by simply changing the composition of the NW suspension used for each flow step. For example, it should be possible to assemble directly and subsequently address individual nanoscale devices using our approach with n-type and p-type NWs, in which the NWs act as both the wiring and active device elements (see below).

Control of periodicity

The above results demonstrate clearly the power of the fluidic assembly approach, although to enable systems organization with greatest control requires in many cases that the spatial position also be defined. To realize this additional constraint on the assembly process, we have explored complementary chemical interactions between chemically patterned substrates and NWs (Fig. 26A). Substrates for alignment are first patterned with two different functional groups, with one of the functional groups designed to have a strong attractive interaction with the NW surface, and then, following flow alignment, regular, parallel NW arrays with lateral periods the same as those of the surface patterns are produced (Fig. 26D). These data demonstrate that the NWs are preferentially assembled at positions defined by the chemical pattern, and moreover, show that the periodic patterns can organize the NWs into regular superstructures. In addition, periodic crossed NW arrays can also be envisioned using a substrate with a crossed pattern of chemical functionality.

Assembly of periodic NW arrays. (A) Schematic view of NW assembly onto a chemically patterned substrate. (B, C) Parallel arrays of GaP NWs aligned on poly (methylmethacrylate) (PMMA) patterned surface with 5 and 2 mm separation. (D) Parallel arrays of GaP NWs with 500 nm separation obtained with a patterned SAM surface.

Fig. 26 Assembly of periodic NW arrays. (A) Schematic view of NW assembly onto a chemically patterned substrate. (B, C) Parallel arrays of GaP NWs aligned on poly (methylmethacrylate) (PMMA) patterned surface with 5 and 2 mm separation. (D) Parallel arrays of GaP NWs with 500 nm separation obtained with a patterned SAM surface.

It is important to recognize that the patterned surface alone does not provide good control of the 1D nanostructure organization. Assembly of NTs[70,71] and NWs on patterned substrates shows that 1D nano-structures align with bridging and looping structures over the patterned areas and show little directional control. Our use of fluidic flows avoids these significant problems and enables controlled assembly in one or more directions. By combining this approach with other surface patterning methods, such as phase separation in diblock copolymers[72] and spontaneous ordering of molecules,[73] it should be possible to generate well-ordered NW arrays without the limitations of conventional lithography.

Future Directions

The above data demonstrate clearly ordering of NW structures over multiple length scales—organization of nanometer diameter wires with 100 nm to micrometer scale separations over millimeter scale areas. This hierarchical order can readily bridge the microscopic and macroscopic worlds, although eventual device formation still requires conventional lithography to define metallic contact electrodes to the NWs. It is possible to eliminate this step by direct assembly of NWs onto predefined metallic electrode arrays[74] that have been deposited by either via conventional or unconventional (e.g., microcontact printing or imprinting methods) lithography techniques. Lastly, it will also be beneficial to develop further these approaches in the future to enable more complex assembly, such as the selective parallel assembly of two or more electronically distinct NWs and/or NWs with different lengths.

INTEGRATED NANOWIRE DEVICES

The ability to synthesize rationally NWs with controlled electronic properties, to demonstrate individual functional NW devices, and to assemble NWs into regular arrays has enabled us to explore in unprecedented depth the next level of hierarchy in the bottom-up approach to nanoelectronics—that is, integrated device arrays.

Integrated Cross Nanowire p-n Junctions and Transistors

To achieve integrated functional device arrays requires high yield and high reproducibility of individual devices with controllable functional properties. In order to assess this issue, we have studied a large number of p-n junctions assembled from p-Si NWs and n-GaN NWs (Fig. 27A).[35] I-V measurements made on over 100 of crossed p-Si/n-GaN NW devices show that over 95% of the junctions exhibit current rectification with turn-on voltages of around 1.0 V.

Crossed NW nanodevice elements. (A) Turn-on voltage distribution for crossed NW junctions. The top-left inset shows histogram of turn-on voltage for over 70 as-assembled junctions showing a narrow distribution around 1 V. The top-right inset shows an example I-V response for low and high turn-on voltage elements. The inset in top-right inset shows a SEM image of a crossed NW device. Scale bar, 1 mm. (B) I-V behavior for a 4(p) x 1(n) multiple junction array. The four curves represent the I-V for each of the four junctions and highlight reproducibility of assembled device elements. The inset shows an example of a multiple crossed NW device. (C) Transfer characteristics of four cNW-FET arrays. The inset shows conductance (G) vs. Vg (Vsd = 1V) for one cNW-FET.

Fig. 27 Crossed NW nanodevice elements. (A) Turn-on voltage distribution for crossed NW junctions. The top-left inset shows histogram of turn-on voltage for over 70 as-assembled junctions showing a narrow distribution around 1 V. The top-right inset shows an example I-V response for low and high turn-on voltage elements. The inset in top-right inset shows a SEM image of a crossed NW device. Scale bar, 1 mm. (B) I-V behavior for a 4(p) x 1(n) multiple junction array. The four curves represent the I-V for each of the four junctions and highlight reproducibility of assembled device elements. The inset shows an example of a multiple crossed NW device. (C) Transfer characteristics of four cNW-FET arrays. The inset shows conductance (G) vs. Vg (Vsd = 1V) for one cNW-FET.

Moreover, the turn on voltage of such crossed p-n junction can be controlled naturally and selectively within the framework of bottom-up approach to fabrication. Specifically, high turn-on voltage junctions can be reproducibly formed by increasing the oxide layer thickness at the junctions by either thermal oxidation of the Si NWs prior to assembly or by Joule heating of specific device elements by passing a high current through a junction in air.

Reproducible assembly of crossed NW structures with predictable electrical properties contrasts sharply with results from NT-based device, and has enabled us also to explore the assembly and properties of integrated p-n junction arrays. Significantly, electrical transport measurements made on a typical 4 x 1 crossed p-Si/n-GaN junction array (Fig. 27B) show that the four nanoscale cross points form independently addressable p-n diodes with clear current rectification and similar turn-on voltages. These data further demonstrate the high yield and reproducibility of our crossed NW p-n devices. In addition, these crossed NW p-n junction arrays can also function as cNW-FET arrays. The transfer characteristics for an array of four cNW-FETs clearly show that each of these four cNW-FET exhibit highly sensitive gate responses with sharp onset voltages at around 2-3 V (Fig. 27C), where the transfer characteristics can be controlled by varying the doping concentration and other characteristics of the NWs used in the assembly process (see below).

Nanowire Logic Circuits

The controlled high-yield assembly of crossed NW p-n diodes and cNW-FETs with attractive device characteristics, such as high gain, enables the bottom-up approach to be used for assembly of more complex and functional electronic circuits, such as logic gates. Logic gates are critical blocks of hardware in current computing systems that produce a logic-1 and logic-0 output when the input logic requirements are satisfied. Diodes and transistors represent two basic device elements in logic gates.[75] Transistors are more typically used in current computing systems because they can exhibit voltage gain. Diodes do not usually exhibit voltage gain, although they may also be desirable in some cases;[35,75] for example, the architecture and constraints on the assembly of nanoelectronics might be simplified using diodes since they are two-terminal devices, in contrast to three-terminal transistors. In addition, by combining the diodes and transistors in logic circuits, it is possible to achieve high voltage gain, while simultaneously maintaining a simplified device architecture. To demonstrate the flexibility of these NW device elements, we have investigated both diode- and FET-based logic.

Logic OR gate

A two-input logic OR gate output is HIGH if either or both of the inputs are HIGH. This basic OR gate can be realized using a 2(p) x 1(n) crossed p-n junction array with the two p-Si NWs as inputs and the n-GaN NW as the output (Fig. 28A). The output-input (Vo—V) voltage response (Fig. 28B) of a typical device shows that Vo increases linearly with Vi when one input is set low (0 V) except for the region near 0 V. This low response region is due to the finite turn-on voltage of the p-n diodes, and produces a logic output typically 0.4-0.2 V less than the input voltage. Small reductions in Vo do not affect the operation of our logic gates because the low turn-on voltage contributions are reproducible and can be readily accounted for in defining the 0 and 1 states. The Vo—Vi data also show a nearly constant high output when the second input is set high (5 V). For example, the output voltage vs. four possible logic address levels, which are 00, 10, 01 and 11 (Fig. 28C), shows that the output is low (logic-0) when both input voltages are low (0 V), and the output is high (logic-1) when either or both of the input voltages are high (5 V). The experimental truth table for the 1 x 2 crossed NW device (Fig. 28D) summarizes the input-output response and confirms that this NW device behaves as a logic OR gate. We also note that assembly of more p-n diodes would produce in a very straightforward and scalable way multiple input OR gates, that is, a 1 x n diode array for an n-input OR gate.

Logic OR gate. (A) Schematics of logic OR gate constructed from a 2 x 1 crossed NW p-n junction. The insets show an SEM image of a device (scale bar, 1 mm) and the symbolic electronic circuit. (B) Output-input (Vo—Vi) relation. (C) The output voltage vs. the four possible logic address level inputs: (0,0); (0,1); (1,0); (1,1). (D) The experimental truth table for the OR gate.

Fig. 28 Logic OR gate. (A) Schematics of logic OR gate constructed from a 2 x 1 crossed NW p-n junction. The insets show an SEM image of a device (scale bar, 1 mm) and the symbolic electronic circuit. (B) Output-input (Vo—Vi) relation. (C) The output voltage vs. the four possible logic address level inputs: (0,0); (0,1); (1,0); (1,1). (D) The experimental truth table for the OR gate.

Logic AND gate

A two-input logic AND gate output is HIGH only if both inputs are HIGH. We have assembled such two-input AND gates from 1(p-Si) x 3(n-GaN) multiple junction arrays (Fig. 29A). In these structures, a p-Si NW is biased at 5 V; two GaN NWs are used as inputs and the third is used as a gate with a constant voltage to create a resistor by depleting a portion of the p-Si NW. The Vo—Vi data (Fig. 29B) shows constant low Vo when the other input is low, and nearly linear behavior when the other input is set at high. Correspondingly, logic-0 is observed from this device when either one or both of the inputs are low (Fig. 29C), since Vi = 0 corresponds to a forward biased, low resistance p-n diode that pulls down the output. The logic-1 is observed only when both inputs are high, since this condition corresponds to reverse biased p-n diodes with resistances much larger than the constant resistor; that is, little voltage drop across the constant resistor and a high voltage is achieved at the output. The experimental truth table for the NW device (Fig. 29D) summarizes the input-output response and confirms that this device functions as a logic AND gate.

Logic NOR gate

FET-based logic NOR gates have been studied using assembled 1(p-Si) x 3(n-GaN) cNW-FET arrays (Fig. 30A). Typically, NOR gates were configured with 2.5 V applied to one cNW-FET to create a constant resistance —100 Mohms, and with the p-Si NW channel biased at 5 V. The two remaining n-GaN NW inputs were used as gates for two cNW-FETs in series. In this way, the output depends on the resistance ratio of the two cNW-FETs and the constant resistor. The Vo—Vi relation (Fig. 30B) shows constant low Vo when the other input is high, and a nonlinear response with large change in Vo when the other input is set low. The logic-0 is observed when either one or both of the inputs is high (Fig. 30C). In this case, one or both of the transistors are off and have resistances much higher than the constant resistor, and thus most of the voltage drops across the transistors. A logic-1 state can only be achieved when both of the transistors are on, that is, both inputs low. Analysis of the Vo—Vi data demonstrates that these two-input NOR gates routinely exhibit gains in excess of 5, which is substantially larger than the gain reported for complementary inverters based on Si NWs[34] and carbon NTs.[25] High gain is a critical characteristic of gates since it enables interconnection of arrays of logic gates without signal restoration at each stage. The experimental truth table for this NW device (Fig. 30D) summarizes the Vo—Vi response and demonstrates that the device behaves as a logic NOR gate. Lastly, these multiple input logic NOR gates can be configured as simple NOT gates (inverters) by eliminating one of the inputs.

Logic AND gate. (A) Schematic of logic AND gate constructed from a 1 x 3 crossed NW junction array. The insets show a typical SEM image (bar, 1 mm) of the assembled AND gate and symbolic electronic circuit. (B) Output-input (Vo—Vi) relation. (C) The output voltage vs. the four possible logic address level inputs: (0,0); (0,1); (1,0); (1,1). (D) The experimental truth table for the AND gate.

Fig. 29 Logic AND gate. (A) Schematic of logic AND gate constructed from a 1 x 3 crossed NW junction array. The insets show a typical SEM image (bar, 1 mm) of the assembled AND gate and symbolic electronic circuit. (B) Output-input (Vo—Vi) relation. (C) The output voltage vs. the four possible logic address level inputs: (0,0); (0,1); (1,0); (1,1). (D) The experimental truth table for the AND gate.

Logic NOR gate. (A) Schematic of logic NOR gate constructed from a 1 x 3 crossed NW junction array. The insets show an example SEM image (bar, 1 mm) and symbolic electronic circuit. (B) Vo—Vi relation; the slope of the data shows that device voltage gain is larger than 5. (C) The output voltage vs. the four possible logic address level inputs. (D) The measured truth table for the NOR gate.

Fig. 30 Logic NOR gate. (A) Schematic of logic NOR gate constructed from a 1 x 3 crossed NW junction array. The insets show an example SEM image (bar, 1 mm) and symbolic electronic circuit. (B) Vo—Vi relation; the slope of the data shows that device voltage gain is larger than 5. (C) The output voltage vs. the four possible logic address level inputs. (D) The measured truth table for the NOR gate.

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