Circuit Design (GPS) Part 9

Floor Planning and Chip Layout Considerations

Figure 3-53 shows the microphotograph of the entire RF front-end chip. The chip size is approximately 2800x3000pm2 and it is a PAD-limited design. Due to the high frequency of the incoming signal, many layout issues may affect the performance of the receiver. These may include, for example, coupling through the substrate, placing components and PADs, and so on.

Much attention has been given to these issues during the placement of the different blocks. The PLL is placed at the top-left and the RF mixer at the bottom-left. The LNA is placed at the bottom-right, far away from the noisy pulse swallow divider of the PLL. In this manner, the performance of the LNA is not degraded. All signal PADs are placed between AC ground PADs. All PADs are installed by stacking metal layers from metal 1 to metal 4, except for RF PADs, where only metal 4 has been used in order to reduce the PAD parasitic capacitance. All PADs are also electrostatic discharge (ESD)-protected. RF pads are installed using an analogue ESD-protection circuit with a very low and almost constant input capacitance, high-ESD level, and no series resistance[Ming-Dou02]. This was done to minimise performance degradation of the front-end due to the ESD protections. The performance of the implemented ESD structures are 2kV for the HBM standard and 300V for the MM standard. Figure 3-54 shows the implemented RF ESD protection with the input diodes and the clamping circuit.


GPS and Galileo RF Front-End IC microphotograph

Figure 3-53 GPS and Galileo RF Front-End IC microphotograph

ESD-protection circuit for analogue PADs

Figure 3-54 ESD-protection circuit for analogue PADs

Digital PADs are employed with standard ESD-protection circuits coming from the input/output (I/O) cells supplied by the foundry. Analogue and digital grounds are also isolated. Large substrate contacts and guard rings separate the different blocks to prevent parasitic coupling. A symmetric layout has been performed in each component (LNA, RF mixer, PLL, etc.) to keep the signal path truly differential. This allows the effect of the voltage supply and ground parasitics to be minimised and the harmonic distortion of the VCO to be reduced. Special attention has been paid to the LC tank layout to minimise the parasitic resistance and capacitance of the connection tracks. A careful layout is also required for the pulse swallow divider and the prescaler, to reduce the signal delay in their feedback loops.

The chip has been packaged in a commercial plastic TQFP 48-pin package. The description for the pins is shown in Table 3-18 and Figure 3-55. Different power supplies and ground pins are specially made for the different parts of the front-end. This has been done to avoid noise coupling among all of them, especially between the sensitive RF blocks, such as the LNA, and the digital noisy blocks, such as the clock output buffers or PLL divider. This is also suitable for testing the final chip. Thereby, 10 pins are located for voltage supply: VDD_IF, VDD_LOGIC2, Vdd_BUFFER, Vdd_LOGIC, Vdd_LNA, Vdd_RF, Vdd_VCO, Vdd_PRE, Vdd_LOGIC, and VDD_XTAL. Regarding the ground pins, there are 16: two for GND_IF, GND_LOGIC2, GND_BUFFER, and GND_LOGIC; three for GND_LNA; two for GND_RF; four for GND_PLL; and two for GND_XTAL. There are two internal grounds: one analogue and one digital. As presented in Figure 3-56.

TABLE 3-18 Front-end IC pins and description

PIN

Symbol

Description

1

vdd_xtal

Power supply

2

vdd_logic

Power supply

3

LF_2

Loop filter

4

vdd_pre

Power supply

5

GND

Ground

6

LF_1

Loop filter

7

vdd_vco

Power supply

8

GND

Ground

9

GND

Ground

10

IF+

Mixer output

11

IF-

Mixer output

12

GND

Ground

13

GND_RF

Ground

14

RF_IN+

RF amp. input

15

RF_IN-

RF amp. input

16

GND_RF

Ground

17

vdd_rf

Power supply

18

LNA_OUT

LNA output

19

GND_LNA

Ground

20

vdd_lna

Power supply

21

GND_LNA

Ground

22

LNA_IN+

LNA input

23

LNA_IN-

LNA input

24

GND_LNA

Ground

25

GC

LNA gain control

26

AS_OUT

Antenna sensor output

27

AS_2

Antenna sensor input

28

AS_1

VDD antenna supply

29

Vdd_logic

Antenna power supply

30

GND_LOGIC

Ground

31

Vdd_buffer

Power supply

32

GND_BUFFER

Ground

33

DATA

Data

34

CLOCK

Clock

35

GND_LOGIC2

Ground

36

Vdd_logic2

Power supply

37

CE2

Chip enable (no data)

38

CE1

Chip enable

TABLE 3-18 Front-end IC pins and description

PIN

Symbol

Description

39

F_SELECT

Frequency selector

40

GND_IF

Ground

41

IF-

Limiting amp. output

42

IF+

Limiting amp. output

43

GND_IF

Ground

44

vdd_if

Power supply

45

GND_XTAL

Ground

46

XTAL_IN

Crystal input

47

XTAL_OUT

Crystal output

48

GND_XTAL

Ground

Figure 3-56 the RF amplifier mixer and the LNA ground and supply pads use double bonding to reduce parasitic bondwire inductance and improve stability of the RF amplifiers. Three pins have been defined for the control logic, as shown in the previous section. The rest of the pins (17) are input or output pins related to the signal path, crystal, and loop filter of the PLL, and gain selection pins for the LNA. The input signal of the receiver is a single-ended signal at LNA_in+ (LNA_in- is connected to an AC ground through a capacitor), while the outputs of the front-end are the navigation DATA and CLOCK.

Pin package layout

Figure 3-55 Pin package layout

Floor-planning and bonding diagram

Figure 3-56 Floor-planning and bonding diagram

Moreover, intermediate pads have been included in the design to check different points of the front-end. Measurement of some components of the circuit separately can be carried out with the test mode available. In this way, the designer can save time and money, as one design can validate the different parts and the whole as one.

External Components

Although the design of the front-end is considered highly integrated, some external components are required, apart from coupling and decoupling capacitors or impedance-matching inductors and capacitors. The required external components include the antenna, the 16.368MHz quartz crystal (TCXO), RF SAW filters, IF filters, and the loop filter.

The antenna can be either active or passive. The RF SAW filters are located between the LNA and the down-conversion stage and optionally between the antenna and the LNA. The target is to block adjacent jamming signals that could compromise the performance of the front-end.

The design example utilises the Murata RF SAW filters DFCB21G57LDJAB-TT1 next to the antenna and the NSVA352 from the NJR Corporation between the LNA and the down-conversion stage.

Summary

The circuit design flow of a GPS and Galileo front-end has been explained and a design example has been successfully carried out. The designs and post-layout simulation results of every block of the front-end have been presented. Some specifications, such as the gain of the LNA, have not been met. However, this has been compensated for by other blocks such as the IF, which has a higher gain than specified. Moreover, estimated input offset of the ADC during the system analysis was four times higher than the simulated one. Therefore, less stringent specifications could be applied to the design.

The proposed floor-planning minimises the RF signal path length and the coupling between the critical blocks. In addition, 48 pads are defined and located for the packaging of the entire front-end. Moreover, ESD protections have been added to the design and the control logic has been defined to control the various operations of the front-end. Finally, required external elements such as RF SAW filters have been selected.

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