PanelLink™ and TMDS™
In the mid-1990s, a small Silicon Valley company, Silicon Image, Inc., introduced its “PanelLink™” interface system, intended as an alternative to the LVDS interface of National Semiconductor and Texas Instruments. Conceptually, PanelLink was similar to LVDS – a flat-panel interface system which serialized the data to be transmitted onto several differential data pairs, and sent this data along with a separate clock (on its own differential pair) to the receiver. However, PanelLink differed from LVDS in several significant aspects.
The most obvious change is a reduction in the number of data pairs; the basic PanelLink interface uses three data pairs rather than four, while still retaining the capacity for carrying 24 bits of video data per clock. Unlike the LVDS system, then, PanelLink isolates the three primary color channels, assigning one to each data pair. Next, the data is encoded prior to serialization, using a Silicon Image proprietary technique. This is an 8-10-bit encoding which is designed to both minimize the number of transitions on the serial lines, while also DC-balancing these lines. This encoding results in the data pair bit rate being 10x the original pixel clock rate, as opposed to the 7x rate of the original LVDS design. At the receiver, another difference between the two systems is found. In the PanelLink™ receiver, the clock is used to generate the 10x clock needed to recover the data, but the 10x clock is produced in several versions with different phase relationships to the original. These are used by the data receivers to independently recover and deserialize the data, permitting each data pair to in effect be independently resynchronized to the clock. This gives the PanelLink system considerable tolerance to data-to-clock or data-to-data (between data pairs) skew, typically up to ±/ the original pixel clock period. Finally, the PanelLink interface is not truly a voltage-differential system. As shown in Figure 10-5, this interface actually operates by “steering” a fixed current between the two lines of the pair. Using a fixed current rather than a fixed voltage provides some obvious advantages for a long-distance interconnect, but results in another subtle distinction. The PanelLink system requires an additional physical connection for each pair, for the return current path. (In practice, many standards using this system now define shared return paths for multiple data lines.) As originally commercialized by Silicon Image, the exact current level – and therefore the voltage swing across the standard 100-Ω terminating impedance – was not fixed, but rather would be set in each application through external components. Later, however, the demands of monitor interface standards lead to the current being set at 12 mA (the maximum allowed in the original transmitters) in most specifications. This results in a nominal 500 mV swing on the signal lines (1.0V differential).
Figure 10-5 The Transition-Minimized Differential Signalling (TMDS) interface. This simplified view of the driver and receiver circuits, shown as used in a monitor interface application, illustrates how the electrical connection operates by steering current between the two conductors of the pair.
In 1995, the PanelLink interface came to the attention of a VESA committee working on the problem of standardizing a digital interface for monitors. Due to its advantages for longer interconnects, as needed for monitor applications, the system was chosen as the basis for the new monitor standard, and the basics of the PanelLink system included as a part of the VESA specification. To distinguish the standard version of the interface from the products offered by Silicon Image, the name “Transition Minimized Differential Signalling,” or TMDS, was adopted. VESA soon published two standards based on TMDS: the “Plug & Display,” or “P&D,” monitor interface,and a new panel-level interface standard, FPDI-II. The FPDI-II standard was never widely adopted, and standardization of panel-level interfaces had to wait for the later SPWG specifications (above). But Panel-Link/TMDS’ use in the P&D standard set the stage for further development of digital monitor standards based on this system.
Use of TMDS as a monitor connection raised an additional concern. In the case of an interface between physically separate products, as with a monitor and its host system, there is no guarantee that the reference or “ground” potential will be the same, and therefore no guarantee that supply voltages of even the same nominal level will actually be compatible. This results in the possibility of problems for interfaces using DC connections; in the case of TMDS, there is a possible problem if the transmitter and receiver supply voltages differ by more than two diode drops in many designs. This would be a relatively rare occurrence in most cases, and systems have been successfully built using a DC-connected TMDS interface (the difference in transmitter and receiver supply voltages is generally limited by the specifications applicable to such systems, typically to not more than 0.6 V). However, the VESA P&D and later monitor-oriented specifications suggested the use of either capacitive or inductive AC coupling at the receiver to avoid any possible problems. In notebook applications, where a common power supply could be assumed for both the receiver and transmitter, there is no potential for this problem, and so direct coupling is the norm (Figure 10-6).
In the first products provided by Silicon Image, the PanelLink interface supported pixel clocks up to 65 MHz, competing with the LVDS components available at the time. Later speed increases raised the upper limit to 85 MHz, then 112 MHz, and finally 165 MHz, in the fastest TMDS products currently available. There has been some indication that further increases in speed may be possible, to rates above 200 MHz, but for now interface standards using TMDS also allow for additional data pairs, as was done with LVDS, when increased data capacity is required. Silicon Image, Inc., has also licensed the basic intellectual property needed for the implementation of the interface to numerous other companies, so that compatible transmitters and receivers are now available from multiple sources.
Figure 10-6 When used in a notebook application, or a similar situation in which the receiver and transmitter share the same power supply, the TMDS interface has no problem with potential voltage mismatches between the two, and direct coupling of the data and clock pairs may safely be used.
GVIF™
A relative newcomer to the market, Sony’s Gigabit Video Interface (GVIF) product line is in its present form aimed at the lower end of the computer market and at digital television. GVIF is also a differential, serial digital interface, but one which uses only one pair of physical conductors. In this system, 24-bit (per pixel) data is encoded (using a proprietary algorithm) and serialized by the transmitter. The data encoding is such that the transmitted data stream is “self-clocking”, i.e., the pixel clock can be derived from the serial stream at the receiver, and used to deserialize and decode the data, and present it at the receiver outputs. The maximum 65 MHz pixel clock rate limits the current system not higher than approximately the 1024 x 768 format at CRT-like timings, although there is certainly sufficient capacity for consumer digital television or digital HDTV, at least in compressed form. To date, no industry standards have been written around the GVIF system, although there has been some interest in basing a standard for “head-mounted” or “eyeglass” displays on it.
Digital Monitor Interface Standards
Through the 1990s, the growing interest in non-CRT displays as desktop PC monitors – and particularly the increasing importance of the LCD monitor – led to several attempts at digital interface standards for this market. While only one of these is currently seeing any significant degree of success, a look at the history of digital monitor interface development through the past decade is very useful in order to understand how this latest standard was shaped.
The VESA Plug & Display™ Standard
Soon after the introduction of the Enhanced Video Connector (EVC) by VESA in 1995, several of the companies which had been involved in the development of that standard began to discuss the possibility of extending the EVC concept to support a digital display interface. What resulted was the VESA “Plug & Display” standard (the name being a play on the “Plug & Play” concept being promoted at the time), which was first released in 1997. Plug & Display, or “P&D” as it was more commonly called, retained a significant degree of compatibility with the original EVC design, and in fact the original EVC was later incorporated into the Plug & Display standard as “P&D-A” (for analog-only).
The P&D connector (Figure 10-7; pinout shown in Figure 9-13) retained the same size and basic shape of EVC, and in one version (P&D-A/D) retained the “Microcross™” analog video section. The 3-row, 10-column field of pins was also retained, but with the analog audio I/O and video input pins now redefined for the support of a single channel (3 data pairs plus one clock pair) of the TMDS digital interface. (The PanelLink interface from Silicon Image, Inc., was standardized and renamed “TMDS” by VESA as part of the P&D effort.) The P&D standard also introduced the concept of “hot plug detection,” whereby the host system could detect the disconnection and reconnection of a display at this connector. This was required by the dual video interfaces supported; without such a scheme, the host would have no way of knowing, for example, that an analog-input display had been disconnected and replaced by one using the digital interface. Detecting such an event permits the host to ID the display upon connection, rather than simply at system power-up, and re-set the graphics system outputs to drive the new display.
Figure 10-7 The VESA Plug & Display Connector, or “P&D,” was a modification of the original VESA Enhanced Video Connector, with the intention of supporting both analog and digital display interfaces on a single physical connector.
The Plug & Display standard also made a slight change to the connector shell design from the original EVC. This simple change made P&D a full connector system, permitting hosts to readily support either the digital interface, analog, or both, simply by using the proper connector. Analog-input displays, using the original EVC plug, would connect only to host providing the EVC (now “P&D-A”) or the combined-output “P&D-A/D” receptacles. Similarly, digital-input displays, using the new shape plug, would connect to either a P&D-A/D or the new digital-only (“P&D-D”) receptacles. This ensured that a display could only physically connect to a host capable of supporting it. (A proposed extended P&D, which would add a separate section to the connector for extending the TMDS support to two channels, was never developed.)
Despite these new features, the P&D system saw only limited acceptance. The biggest concern expressed by most potential users was the optional support for the IEEE-1394 and USB interfaces. Display manufacturers could not be sure that either would be supported on any given host system, and similarly system manufacturers were not willing to design support for either in without suitable displays being available. While the industry struggled to resolve this, two new options were developed – and interest in the P&D system declined.
The Compaq/VESA Digital Flat Panel Connector – DFP
While discussion continued regarding the use of P&D’s “optional” interfaces, there was still a need for a simple digital interface that could be easily implemented to support non-CRT displays. Compaq Computer introduced what it called the “DFP” connector – for “Digital Flat Panel” – on several PC products in the summer of 1997. DFP was intended as a bare-minimum implementation of a digital display interface, one which could easily be used in addition to the existing analog interface provided by the “VGA” connector.
Using a 20-pin “micro delta ribbon,” or “MDR” connector (from a family developed by 3M), the DFP specification supported a single channel of the TMDS interface, the “hot plug” system of P&D, and the basic VESA Display Data Channel (DDC) connection for display ID. DFP saw some success as a standard connection for LCD monitors, but was seen by many as only a short-term solution to be used alongside the VGA connector – until both were replaced by P&D, or by whatever the industry finally determined would be the longterm solution. DFP was later adopted as a VESA standard, in essentially the same form as originally introduced (Figure 10-8).
Figure 10-8 The Compaq (later VESA) Digital Flat Panel (DFP) connector. Used by permission of VESA.
The Digital Visual Interface™
In order to finally establish a new video interface standard which would be acceptable to both the major systems manufacturers and display makers, the Digital Display Working Group (DDWG) was formed in 1999. The core members, known as the DDWG Promoters’ Group, was made up of seven of these companies: Compaq, Fujitsu, Hewlett-Packard, IBM, Intel, NEC, and Silicon Image. The new standard, called the Digital Visual Interface (DVI™ 1.0) was also to be based on Silicon Image’s PanelLink or TMDS technology, and the connector chosen was very similar to the VESA P&D. The major changes from P&D to DVI included the deletion of the optional IEEE-1394 and USB interfaces, and the additional of a second TMDS data channel (three data pairs), sharing the same clock pair as the basic channel. (The additional data pairs in some cases also share the ground/return connections of the original set.) DVI also raised the question of digital content protection for the first time; while not required under the 1.0 specification, the use of an Intel-proprietary encryption system (High-Definition Content Protection, or HDCP) is officially recognized under DVI.
Physically, the DVI connectors resemble the VESA P&D, although with two fewer columns of pins and a slightly different shell design. This prevents direct physical compatibility between the two, although it is possible to connect P&D and single-channel or analog DVI with the appropriate adapters. Like P&D, DVI defined both a digital-only version (DVI-D), and one which supports both analog and digital interfaces (DVI-I), again via the Microcross™ pseudo-coaxial connector design originated by Molex. Pinouts for both DVI versions are shown in Figure 10-9.
As of this writing, DVI has begun to see fairly widespread adoption as an LCD monitor connection, although it has yet to significantly displace the VGA connector or other options for CRT monitors, either in analog or digital form. There is also considerable interest in the standard as a possible solution for consumer television applications, for example as an interconnect between digital HDTV decoders (“set-top boxes”) and digital-input receivers. The support for digital content protection provided by DVI (the HDCP encryption system) is of particular interest in such applications. However, there remain some open issues within the DVI specification, which are being addressed by a joint effort between the DDWG and several consumer electronics manufacturers and their industry association, the CEA. Among these are the need for audio support and the possibility of alternate color encoding methods, such as a “YUV” or similar encoding rather than the DVI-standard RGB. The DDWG is also working on some implementation concerns which have been raised by the computer industry, such as the use of DVI as a display input connector and the standard means for transitioning between single- and dual-channel TMDS support. The former is a concern due to the possibility of different display capabilities being available depending on whether the analog or digital interface is in use – yet the display can only provide a single set of ID information at a time. The use of the second TMDS channel is also problematic under the current specification. While the DVI 1.0 standard set 165 MHz as the limit for the basic single-TMDS version, it did not set explicit guidelines for managing both single- and dual-channel operation within a given system. The second channel could potentially be used for supporting larger display/image formats, increased “color depth” or both – but how this is to be negotiated between the display and host has not yet been well defined.
Still, even with these minor concerns, DVI at this point represents the interface most likely to win widespread adoption within not only the computer display industry, but beyond it to consumer applications as well. Development of the standard will no doubt continue for some time, but there seems to be enough momentum building behind this latest standard to ensure at least success beyond that achieved by the earlier attempts.
Figure 10-9 The Digital Visual Interface. Both DVI-I and DVI-D pinouts are shown; the connectors are identical, except that the DVI-D is blank in the area of the “MicroCross™” analog connections. Note: the “vertical sync” (pin 8) and “horizontal sync” (pin C4) signals of the DVI-I are for use only by displays using the analog connection; they cannot be used with the digital interface. TMDS pairs 35 comprise a second data channel, for added capacity; its use is optional.
