In this topic, we turn to the most ambitious means available to minimize errors in the face of hardware and software not designed for extraordinary timekeeping. First, we examine the hardware and software components for a precision system clock and evolve an effective design for future systems. Next, we survey timestamping techniques using hardware, driver, and software methods to minimize errors due to media, device, and operating system latencies. Finally, we explore the Institute of Electrical and Electronics Engineers (IEEE) 1588 Precision Time Protocol (PTP), how it is used in a high-speed LAN, and how it and NTP can interoperate. The Parting Shots section proposes a hardware-assisted design that provides performance equivalent to PTP with only minimal modifications to the Unix operating system kernel.
Computer timekeepers live in a world of commodity clock oscillators vulnerable to temperature surges and operating systems vulnerable to scheduling and queuing latencies. Once upon a time, it took 42 jus to read the system clock on a Sun SPARC IPC and up to 22 ms jitter on the Streams driver stack. Now, the nominal latency to read the system clock on a modern computer is only half a microsecond. With proper choice of operating system parameters and scheduling priority, the latency variations can be reduced to this order.
Recall the typical Allan deviation characteristic exhibited in Figure 12.2. Note that the apex of the V-shaped characteristic, the Allan intersection, moves to the left as the phase noise is reduced, given the same frequency noise characteristic. In the MICRO characteristic the apex is about 250 s, representing the ideal averaging time. Improvements since that figure was determined suggest that the phase noise can be reduced by an order of magnitude using the system clock design suggested in Section 15.2. To the extent that the phase noise can be reduced, the time constant can be reduced as well, which reduces the effects of frequency noise. As demonstrated in this topic, this is advisable only with hardware- or driver-assisted timestamps.
A useful benchmark for the current art is an experiment using a PPS signal from a cesium oscillator or GPS receiver hooked up to the kernel PPS discipline. With the poll interval strapped to 8 s, the time constant is about 256 s, which puts a reasonably tight reign on oscillator wander. The results of this experiment with several machines, both old and new, show typical offset and jitter of a few microseconds contributed by the hardware and operating system driver. However, incidental jitter is reduced by three orders of magnitude by the discipline algorithm. While not rigorously justified by statistics, the experiment does suggest a performance bound not likely to be exceeded with commodity computer hardware and operating systems.
Even with the kernel discipline, it is necessary to closely examine the hardware and software components of the system clock to sustain the highest performance without expensive dedicated hardware components. We next explore how this can be done using relatively inexpensive components and closely engineered discipline algorithms. While designs such as this might not appear in commodity computers, they might well be adapted to embedded computers used in spacecraft and measurement applications.
