Biomedical Engineering Reference
In-Depth Information
Fig. 1.7 Dielectric noise reduction in solid-state Al
2
O
3
nanopores (a) Architecture 1 consists of a
45
5 nm thick Al
2
O
3
membranes formed on a low resistivity Si substrate. (b) Architecture
2 consists of a 500 nm thick SiN passivation layer added on top of the Al
2
O
3
film with a 30
m
m
square opening forming the membrane region. PDMS gaskets with 300
m openings were bonded
to the chip to further decrease device capacitance. (c) Architecture 3 consists of a 1.5
m
m
m thick SiN
passivation layer added on top of the Al
2
O
3
film with a patterned 5
m circular opening
constituting the Al
2
O
3
membrane area. This stack was formed on a high resistivity Si wafer
(
m
-cm) (d and e) Impedance magnitude and phase spectra for the various architectures
investigated. By fitting to an equivalent RC circuit, capacitances of 1 nF, 300 pF and 20 pF were
extracted for architectures 1, 2 and 3 respectively (f) Normalized current traces in 1 M KCl,
10 mM Tris, pH 7.5 buffer at an applied voltage of 200 mV for architectures 1, 2 and 3.
Capacitance reduction decreases the peak-to-peak noise from 1.2 nA (architecture 1), to 400 pA
(architecture 2), to 200 pA (architecture 3)
r ΒΌ
10,000
O
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