Biomedical Engineering Reference
In-Depth Information
in the nanopore thereby following Hooge's phenomenological relation rather than on
the surface charge fluctuations and composition of the nanopore surface [
79
,
80
,
82
].
Surface modifications however have been shown to significantly improve the 1/
f
noise
characteristics of nanopores. Chen et al. used an atomic layer deposition process to
coat Si
3
N
4
nanopores with Al
2
O
3
and saw significant reductions in 1/
f
noise [
14
,
15
].
Tabard-Cossa et al. demonstrated a significant reduction in 1/
f
noise by treating
nanopore chips with piranha solution [
86
]. It is therefore likely that 1/
f
noise in
nanopores is a combination of the two mechanisms described previously; that is,
fluctuations in the total number of charge carriers in the nanopore coupled with a
fluctuation in their mobilities due to trapping at surface sites. As expected, 1/
f
noise
was observed in our experiments involving nanopores sputtered in Al
2
O
3
thin films
and were comparable in magnitude to noise levels observed in biological nanopores.
By addressing the surface properties of solid-state nanopores, through either chemical
surface treatment or material choice, improved noise performance may be achieved.
1.3.5.2 Dielectric Noise
Dielectric noise in nanopores is associated with the capacitance of the nanopore
chip and scales linearly with frequency. Nanopores are typically fabricated in
dielectric thin film such as SiO
2
or Si
3
N
4
, anchored on a conductive Si substrate.
These dielectric materials are typically lossy and have a dissipation factor,
D
,
associated with them. Smeets et al. extracted a dissipation factor of 0.27
0.07
for Si
3
N
4
pores, strongly deviating from
D ¼
0 for an ideal capacitor [
80
,
82
].
The dielectric noise can be reduced by minimizing the capacitance of the substrate.
To achieve this, the thickness of the Si substrate can be increased or the fluidic
contact area on the chip can be minimized. Tabard-Cossa et al. selectively patterned
PDMS on Si
3
N
4
chips to reduce the fluidic contact area and thereby minimized
dielectric noise [
86
].
Using various micro-fabrication processes and PDMS fluidic isolation techni-
ques, we achieved noise performance that surpasses the state-of-the-art in Si
3
N
4
technology as reported by Tabard-Cossa et al. [
86
]. Noise reduction was attributed
to a decrease in device capacitance, measured at 20
5pF[
89
] as compared to
device capacitance in Si
3
N
4
structures, which was measured in excess of 300 pF
[
80
,
82
]. Noise performance was further optimized using the three structures
illustrated in Fig.
1.7
. Architecture 1 consisted of 45
5 nm thick Al
2
O
3
mem-
branes formed on a low resistivity Si substrate. Architecture 2 consisted of a 500 nm
thick SiN passivation layer added on top of the Al
2
O
3
layer with a 30
m
m square
opening forming the membrane region. PDMS gaskets with 300
m openings were
bonded to the chip to further decrease device capacitance. Architecture 3 consisted
of a ~1.5
m
m
m thick SiN passivation layer added on top of the Al
2
O
3
layer with a
5
m circular opening containing the Al
2
O
3
membrane area. This stack was formed
on a high resistivity Si wafer (
m
-cm), effective in reducing leakage
currents through the substrate. PDMS gaskets containing a 300
r ¼
10,000
O
m
m opening
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