Solid-State Nanopores: Methods of Fabrication and Integration, and Feasibility Issues in DNA Sequencing - Nanopores: Sensing and Fundamental Biological Interactions - page 184

opening of a nanometre-scale pore in the silicon chip at the tips of the inverted
pyramid. Thus one can stop the etching process promptly and prevent over-etching.
For this study, a 105 undoped silicon wafer (Virginia Semi-

conductor, Inc.) was used. First, a 180 nm layer of Si 3 N 4 was grown by standard
Plasma Enhanced Chemical Vapor Deposition (PECVD) or Low Pressure Chemical
Vapor Deposition (LPCVD) on both sides of the wafer and was used as an etching
mask. For inverted pyramid fabrication, the front side of the Si wafer had an
exposed area of 30

m m thick < 100 >

m square (pattern generated by photolithography)
with Si 3 N 4 layer removed by CF 4 plasma etching. On the back side, a larger exposed
area (1 mm 1 mm) was patterned by the same method. The front and back
patterns were aligned such that

m m 30 m

the two square patterns were approximately

concentric.
The exposed bare silicon in the squares, both front and back, were etched into
invert pyramid shapes in 45% (w/w) KOH at 85 C. The etching was continued
until the inverted pyramid on the front surface attained a sharp tip. At this point, the
tip of the front inverted pyramid had not reached the back surface (the top of the
pyramid on the back).
After extensive cleaning with de-ionized (DI) water, the silicon-chip sample was
attached using a chemical resistant wax (Apiezon W) on an opening of a Teflon tube
such that the front side with the sharp invert pyramid was in contact with an ionic
solution (1 M KCl), while the back side with large area of bare silicon was exposed
to KOH etchant. As shown in the inset of Fig. 8.5 , one Pt electrode was inserted in
each solution, respectively, and they were connected to a power supply and an
ammeter in series.
The first key step in fabricating a nanopore is to control the opening process.
Here, one monitors the opening processes by measuring the time dependence of the
electrical current flowing through the silicon chip. However, there is a large zero-
bias electric current spontaneously flowing through the silicon chip as soon as the
silicon sample is brought into contact with two electrolytes (KCl and KOH). This is
due to electrons generated at the interface of Si and KOH solution during the
etching process, Si + 4OH !

Si (OH) 4 +4e . Fortunately it was found that
the zero-bias current can be minimized by applying a voltage to cancel out the
electrochemical potential difference between KCl/Si and KOH/Si surfaces.
In contrast, there is no such background current when the materials being etched
are insulating such as polyethylene terephthalate (PET), and Kapton.
In the study of Park et al. [ 9 ], a voltage of ~800 mV is applied with cathode being
the Pt electrode in KCl, and anode in KOH. The etching rate of KOH in

at
room temperature is approximately 18 nm/min, which is slow enough such that the
etching process can be stopped manually (or by robotic arms). While the back side of
the silicon chip is being etched by KOH, the electric current across the chip is
monitored and recorded in real time. When a pore is etched through at the tip of the
inverted pyramid, the electric current increases sharply, as shown in Fig. 8.5 .
Depending on the desired pore size, at certain current level, one can terminate the
etching process, and remove the silicon-chip sample from the electrochemical cell
and clean it with DI water.

< 100 >