Simulation of Electronic Sensing of Biomolecules in Translocation Through a Nanopore in a Semiconductor Membrane - Nanopores: Sensing and Fundamental Biological Interactions - page 154

7.2 Motivation: Device Structure Description

A synthetic nanopore in a SOS capacitor is schematically illustrated in Fig. 7.1
(center panel). It consists of a very thin (

5 nm) SiO 2 membrane, sandwiched
between two heavily doped silicon layers (one polycrystalline silicon; the other
crystalline silicon) sitting on a thicker oxide layer, and covered by a thin oxide
layer. A nanopore of diameter smaller or equal to 2 nm is etched through the
membrane layers in the thinnest (center) part of the structure. The details of
the fabrication process are described elsewhere [ 14 ]. The whole structure is
immersed in a KCl buffer solution containing two external electrodes under electric
bias, which can also measure the ionic current flowing through the nanopore, as
proposed in other DNA molecule detectors [ 4 , 10 , 14 ]. The device membrane forms
a nanoscale electric capacitor, which can record voltage fluctuations induced by the
sequence of charges carried by a DNA strand when it

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translocates through

the nanopore.
The use of semiconductor materials allows also direct integration of nanoscale
Metal-Oxide-Semiconductor (MOS) amplifiers with high sensitivity on the nano-
pore layer structure to improve the voltage signal. Owing to the short distance
between the two capacitor plates, one can expect the voltage signal to be character-
istic of the electronic structure of the DNA molecule, potentially with resolution up
to a single base pair when the capacitor dielectric and nanopore diameter are ~1 nm.
Because of the solid-state nature of the nanopore, the system is robust. It operates
over a wide range of electrolyte concentrations, pH [ 25 ], temperature and external
voltages [ 26 ], unlike proteinaceous pores that operate under stringent chemical and
electrical conditions. This last consideration provides wide latitude to optimize the
system for better detection.
The membranes are manufactured using conventional semiconductor processing
techniques, starting with a 200 mm Semiconductor-Oxide-Insulator (SOI) wafer
with a silicon layer 20 nm thick on a 150 nm thick buried oxide. Rapid thermal
oxidation of the heavily-doped (n -type or p -type) crystalline silicon (SOI) layer is
used to produce a high-integrity gate dielectric 5 nm thick. Subsequently, heavily-

doped polysilicon is deposited on the oxide and chemical-mechanical polishing is
used to reduce the thickness of the poly electrode to about 20 nm (see Fig. 7.1 (center
panel)). A high resolution Transmission Electron Microscope (TEM) micrograph
shows cross-section through the membrane structure in Fig. 7.1 (right panel). A
membrane, comprised of the poly-SiO 2 -silicon capacitor, is formed by creating a
through-wafer via using optical lithography in conjunction with reactive ion and wet
chemical etching on sacrificial layers. After electrical contacts to the top and bottom
silicon electrodes are formed, a nanopore is produced in the membrane using a
tightly focused, high-energy electron beam to sputter atoms from the capacitor. A
top-down lattice image of the 6-7 nm diameter pore through the membrane is shown
in Fig. 7.1 (left panel). The figure shows a TEM of an R p ¼

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0.1 nm radius pore
produced in a poly-SiO 2 -silicon membrane 45 nm thick, taken at a tilt angle of 0 .
This image represents a two-dimensional (2D) projection through the membrane.

3.5