Databases Reference
In-Depth Information
Lower manufacturing costs — This is possible because more processors can be produced
from a standard silicon wafer. This helps to create more powerful and more power-efi cient
processors available at a lower cost, which is benei cial to everyone but especially the data-
base administrator.
The i rst tock release was the Intel Core microarchitecture, which was introduced as the dual-core
“Woodcrest” (Xeon 5100 series) in 2006, with a 65nm process technology. This was followed up
by a shrinkage to 45nm process technology in the dual-core “Wolfdale” (Xeon 5200 series) and
quad-core “Harpertown” processors (Xeon 5400 series) in late 2007, both of which were Tick
releases. The next tock release was the Intel “Nehalem” microarchitecture (Xeon 5500 series),
which used a 45nm process technology, introduced in late 2008. In 2010, Intel released a Tick
release, code-named “Westmere” (Xeon 5600 series) that shrank to a 32nm process technology in
the server space. In 2011, the 32nm “Sandy Bridge” tock release debuted with the E3-1200 series
for single-socket servers and workstations. This was followed up by the “Ivy Bridge” tick release of
the E3-1200 v2 series for single-socket servers and workstations that had a process shrink to 22nm.
Table 2-3 shows the recent and upcoming Tick-Tock releases in the two-socket server space.
TABLE 2-3: Intel Tick-Tock Release History for Two Socket Servers
TYPE
YEAR
PROCESS
SERIES
CODE NAME
Tock
2006
65nm
5100, 5300
Woodcrest, Clovertown
Tick
2007
45nm
5200, 5400
Wolfdale, Harpertown
Tock
2008
45nm
5500
Nehalem - EP
Tick
2010
32nm
5600
Westmere-EP
Tock
2012
32nm
E5-2400, E5-2600
Sandy Bridge-EP
Tick
2013
22nm
TBA (E5-2600 v2?)
Ivy Bridge-EP
Tock
2014
22nm
TBA
Haswell
Tick
2015
14nm
TBA
Rockwell
Tock
2016
14nm
TBA
Sk ylake
Intel Hyperthreading
Intel originally implemented a feature called hyperthreading back in 2002, as part of the NetBurst
architecture in the Northwood-based Pentium 4 processors and the equivalent Xeon family.
Hyperthreading was created to address the frequently wasted processor cycles that resulted when
the central processor in a system waited on data from main memory. Instead of wasting processor
cycles during this wait time, the idea was to have two logical processors inside a single physical core
that could each work on something different when the other logical processor was stalled waiting on
data from main memory.
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