Hardware for Neural Networks - Neural Networks and Micromechanics - page 131

Rachkovskij, M. E. Kussul, and the Japanese company WACOM. The neurocom-
puter was named B-512. Sadao Yamamoto, Masao Kumagishi, and Yuji Katsur-
akhira participated on the Japanese side of the neurocomputer's development.

7.2.1 The Designation of the Neurocomputer Emulator

Usually, computer emulators are used during the development of devices for
checking the functionality of the developed device and for the development of
software before the production of the device itself. During the creation of B-512's
software arose difficulties connected with the fact that access to memory was
complex, and the development of programs was carried out in a low-level language.
Therefore, for program debugging, it was desirable to have open access to the
memory. To eliminate this disadvantage, the neurocomputer emulator was devel-
oped, which was capable of debugging programs. Let us consider in detail the
structure of the emulator.

7.2.2 The Structure of the Emulator

The emulation of the neurocomputer was conducted at the level of neurocomputer
instructions and did not affect the level of separate signals. A change in the state of
all registers and the state of the neurocomputer's memory were considered during
emulation. The following types of instructions were used in the neurocomputer: 1)
shifts; 2) flags set; 3) reading from and writing into memory with the fulfillment of
logical operations; 4) the calculation of “1s”; and so on. Table 7.1 gives the list of
B-512's instructions. The following abbreviations are used: DRAM[] is dynamic
RAM; SRAM 1 [] is static memory for instructions; SRAM 2 [] is static memory for
data; LR 2 ,LR 3 are registers of the logical modules; RG 2 ,RG 3 are registers of the
control unit (CU); CNT 1 , CNT 2 , CNT 3 , CNT 4 are counters. In Table 7.1 , the
following additional designations are accepted:
label is the marker placed in SRAM 1 [ L ];
var is the variable stored in SRAM 2 [ M ];
L is the low-order bits of the register RG 1 of the control unit (CU);
M is the average bits of the register RG 1 of the control unit (CU);
const is the constant placed in L .

The following bitwise operations are realized on the neurocomputer:

A -NOT A;
A & B -A AND B;
A|B -AORB;
A ˆ B -A XOR B.