Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 78

the Instruction Queue (IQ), the load/store queue (LSQ), and the reorder buffer (ROB)
[ 182 ]. As in Albonesi's work [ 7 ] (and later in Buyuktosunoglu et al. [ 42 ]) these structures
are assumed to be physically partitioned into chunks that can be dynamically enabled and
disabled.
The major contribution compared to the previous work is the feedback control technique
they propose for dynamically resizing these structures. Ponomarev et al. argue that feedback
control based on performance metrics such as IPC, or on the number of ready entries, does not
reflect the true needs of a program. All these metrics can be misleading since they are not solely
affected by the instruction queue size but actually depend on many other factors: cache miss
rates, branch misprediction rates, amount of instruction-level parallelism, etc.
Instead, they propose that the occupancy of a structure (the percentage of valid entries) is
the appropriate feedback control metric for resizing. For the three structures that compose the
instruction scheduling mechanisms (IQ, LSQ, and ROB), they show that their occupancies
are positively correlated, meaning that all three should be resized in concert. However, because
the ratios of the occupancies among these structures vary over time, it is imprecise to resize all
three based on the occupancy of a single one (e.g., the IQ). Rather, it is better if each structure
is resized based on measurements of its own occupancy.
The feedback control scheme periodically samples the occupancy and makes decisions
at the end of an update period (which is a multiple of the sampling period). A structure is
downsized by disabling as many partitions as can fit in its empty space (which is determined by
its occupancy measurements). If, however, a structure fills up and the allocation of new entries
is blocked, then it is upsized by powering up more partitions. Upsizing is triggered when
the number of cycles that new entries remain blocked exceeds a certain threshold. Upsizing is
aggressive to limit performance degradation. In simulations for a 4-issue processor, this method
yields power savings for the three structures in excess of 50% with a performance loss of less
than 5%.
4.6.4 Logical Resizing Without Partitioning
Folegnani and Gonzalez take a different path to adapt IQ power 6 to program needs [ 80 ].
Instead of physically segmenting the instruction queue and then disabling large chunks at a
time, they do the following: first, they disable individual IQ entries; second, they limit the
instruction queue's size not physically but logically by limiting the part that can be allocated to
new entries.
6 According to their estimates, instruction queue power accounts for 25% of the total power consumption of a typical
microarchitecture.