Optimizing Capacitance and Switching Activity to Reduce Dynamic Power - Computer Architecture Techniques for Power-Efficiency - page 68

energy for a 64KB L1 cache [ 235 ]. The energy reduction comes, of course, from efficiently
accessing compressed values. The cost of accessing the smaller low-order bit array plus the cost
of accessing the dictionary is less than the cost of accessing the full cache line in a standard
cache organization.

4.4.3 Packing Compressed Cache Lines: Compression Cache
and Significance-Compression Cache
DZC and FVC save power solely by accessing fewer bits for compressed items. In both
techniques, the space freed by compression simply remains empty in the cache. This empty
space can be exploited by squeezing more than one compressed lines in a cache frame [ 237 , 141 ].
This is equivalent to narrow-width operand packing in the datapath and, likewise, is intended
to increase cache utilization . Besides the power savings of accessing compressed values (reading
fewer bits), increasing cache utilization yields indirect power savings since the lower part of the
memory hierarchy is accessed less frequently.

☞ packing techniques : There are two techniques to pack compressed lines in cache frames:

variable packing and fixed packing .

Variable packing aims to maximize the utilization of the available cache space by
compressing and packing a variable number of cache lines into a cache frame. Cache
line boundaries within a frame are not fixed since cache lines can be compressed
to different sizes. This necessitates an indirection for locating the compressed lines
[ 6 , 90 ]. Variable packing is expensive both in terms of power and latency due to
the complex compression and placement of lines in cache frames. It is therefore
best suited for L2 implementations [ 6 ]. The possible power benefit of variable
packing in the L2 comes from increasing the hit ratio, not from accessing the
compressed lines. Variable packing is not a veritable low-power technique since it
is quite expensive on its own. We will not expand further, but for a good discussion
of variable packing, see the work by Alameldeen and Wood [ 6 ] and the work of
Halnor and Reinhardt [ 90 ].

In fixed packing , a preset number of cache lines are packed in a cache frame if they
can be compressed to fit in pre-allocated spaces. Fixed storage requirements come
at the price of reduced opportunities for compression—some cache lines simply do
not compress enough to fit. But in contrast to variable packing, an implementation
based on fixed packing [ 235 , 234 , 141 , 130 ] achieves power benefits not only from
fewer accesses to the next cache level, but also from power-efficient accesses to
compressed data.