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TABLE 4.2: Byte Significance in a 32-bit Word. Adapted from [ 44 ].
Tag
Byte
% of values
(Arbitrary
Significance ( S )
in SPECInt95
Enumeration)
(e for sign extension)
and Mediabench
0
eeeS
61
1
eeSS
14
2
SSSS: NON-COMPRESSED
13
3
eSSS
7
4
SSeS
2
5
SeSS
2
6
eSeS
1
7
SeeS
1
all values is narrow-width using the Brooks-Martonosi 16-bit definition (i.e., only the first
and possibly second bytes are significant). In other words, relaxing the two restrictions of the
original narrow-width definition gives an additional 12% of “compressable” values.
Byte-serial pipelines : A complete pipeline can be built around this significance compression
scheme [ 44 ]. Only significant bytes flow through the pipeline and are operated on. The rest are
carried and stored via their tags. This opens up the possibility of a very low-power byte-serial
pipeline , which is a single byte wide. If more than one significant byte needs to be processed at a
pipeline stage, then this stage simply repeats for the significant bytes. However, the performance
hit on this pipeline is severe: CPI (cycles per instruction) increases 79% over a full width (32-bit)
pipeline. Activity savings range from 30% to 40% for the various pipeline stages.
A significant improvement in performance, without necessarily increasing switching
activity, can be gained by doubling the width of the pipeline from one to two bytes in selected
stages. This is done for the register file read and in the ALU stages which are the major
bottlenecks. In this byte semi-parallel pipeline , the additional byte is enabled if there is more
than one significant byte to be processed. This results in a performance hit over a full-blown
pipeline of just 24% while retaining the 30-40% activity savings.
Increasing the pipeline width to four bytes ( byte-parallel pipeline ) and enabling only the
parts that correspond to the significant bytes of a word, retains most of the activity savings
 
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